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公开(公告)号：US11562789B2
公开(公告)日：2023-01-24
申请号：US17117713
申请日：2020-12-10
Applicant: Infineon Technologies AG
Inventor： David Mueller , Wolf Allers , Christian Peters
Abstract: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.
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公开(公告)号：US20210312979A1
公开(公告)日：2021-10-07
申请号：US17218373
申请日：2021-03-31
Applicant: Infineon Technologies AG
Inventor： Wolf Allers , Jan Otterstedt , Christian Peters
Abstract: Read circuitry for a memory cell of a resistive change memory is suggested, wherein a signal of a bit-line that is connected to the memory cell is compared with a reference signal, and wherein the reference signal is determined based on a first dummy circuit that determines a leakage current of memory cells addressed by the bit-line. Also, a corresponding method is provided.
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3.发明授权公开(公告)号：US10475520B2
公开(公告)日：2019-11-12
申请号：US15821871
申请日：2017-11-24
Applicant: Infineon Technologies AG
Inventor： Jan Otterstedt , Robin Boch , Gerd Dirscherl , Bernd Meyer , Christian Peters , Steffen Sonnekalb
Abstract: A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.
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公开(公告)号：US20150293824A1
公开(公告)日：2015-10-15
申请号：US14252925
申请日：2014-04-15
Applicant: Infineon Technologies AG
Inventor： Christian Peters
CPC classification number: G06F11/2094 , G06F11/1068 , G06F11/1666 , G06F11/20 , G11C16/3445 , G11C29/4401 , G11C29/50004 , G11C2029/0409
Abstract: A method is suggested for processing a target memory, the method comprising the steps of (i) checking the target memory subsequent to an erase operation directed to the target memory; and (ii) replacing the target memory with a spare memory in case a defect is detected.
Abstract translation: 提出了一种用于处理目标存储器的方法，该方法包括以下步骤：（i）在针对目标存储器的擦除操作之后检查目标存储器; 以及（ii）在检测到缺陷的情况下用备用存储器替换目标存储器。
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公开(公告)号：US10937469B2
公开(公告)日：2021-03-02
申请号：US16666425
申请日：2019-10-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Jan Otterstedt , Robin Boch , Gerd Dirscherl , Bernd Meyer , Christian Peters , Steffen Sonnekalb
IPC: G11C7/10 , G06F11/10 , G06F11/25 , G06F12/02 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/34 , H03M13/13 , G11C29/26
Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.
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Patent Agency Ranking
公开(公告)号：US20180158534A1
公开(公告)日：2018-06-07
申请号：US15831439
申请日：2017-12-05
Applicant: Infineon Technologies AG
Inventor： Jan OTTERSTEDT , Robin Boch , Gerd Dirscherl , Bernd Meyer , Christian Peters , Steffen Sonnekalb
CPC classification number: G11C29/34 , G06F11/1048 , G06F11/25 , G06F12/0246 , G11C7/1006 , G11C16/08 , G11C16/105 , G11C16/26 , G11C2029/2602 , H03M13/13
Abstract: In various embodiments, a memory circuit is provided. The memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, wherein each word portion is configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion comprising a plurality of overlay memory cells, wherein each of the plurality of overlay portions comprises an overlay word, wherein the memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, thereby providing, as an output of the read operation, a result of a logic operation performed on the data word and the overlay word.
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公开(公告)号：US20180151244A1
公开(公告)日：2018-05-31
申请号：US15821871
申请日：2017-11-24
Applicant: Infineon Technologies AG
Inventor： Jan Otterstedt , Robin Boch , Gerd Dirscherl , Bernd Meyer , Christian Peters , Steffen Sonnekalb
CPC classification number: G11C29/025 , G11C7/06 , G11C29/12005 , G11C29/702 , G11C29/82 , G11C2029/1202 , G11C2029/4402
Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a plurality of word lines, each word line coupled with one or more memory cells, a plurality of non-volatile marking memory cells, wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells, and a plurality of marking bit lines, each associated with marking memory cells, a plurality of marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.
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8.发明申请Method for Applying Magnetic Shielding Layer, Method for Manufacturing a Die, Die and System 有权应用磁屏蔽层的方法，制造模具，模具和系统的方法公开(公告)号：US20150054102A1
公开(公告)日：2015-02-26
申请号：US13970651
申请日：2013-08-20
Applicant: Infineon Technologies AG
Inventor： Christian Peters , Robert Allinger , Klaus Knobloch , Snezana Jenei
IPC: H01L23/552 , H01L43/12 , H01L43/02
CPC classification number: H01L23/552 , H01L43/02 , H01L43/12 , H01L2924/0002 , H01L2924/3025 , Y10T156/12 , H01L2924/00
Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.
Abstract translation: 提供了一种将磁屏蔽层施加到基板上的方法，其中第一磁屏蔽层粘附到基板的第一表面。 第一膜层粘附到第一磁屏蔽层，第一磁屏蔽层比第一磁屏蔽层比膜层更贴附于第一表面。
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公开(公告)号：US11062761B1
公开(公告)日：2021-07-13
申请号：US16740893
申请日：2020-01-13
Applicant: Infineon Technologies AG
Inventor： Jan Otterstedt , Wolf Allers , Christian Peters
IPC: G11C11/4094 , G11C11/4074 , G11C11/408 , G11C11/4097
Abstract: A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.
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公开(公告)号：US10236041B2
公开(公告)日：2019-03-19
申请号：US15597846
申请日：2017-05-17
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Thomas Kern , Christian Peters
Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.
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