公开(公告)号：US20190114111A1

公开(公告)日：2019-04-18

申请号：US16156046

申请日：2018-10-10

Applicant: Infineon Technologies AG

Inventor： Joel Hatsch ,  Bernd Meyer ,  Jan Otterstedt ,  Steffen Sonnekalb

IPC: G06F3/06 ,  G11C8/08 ,  G06F11/10

Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.

公开(公告)号：US09093128B2

公开(公告)日：2015-07-28

申请号：US13668963

申请日：2012-11-05

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  David Müller

IPC: G11C7/06 ,  H04L9/32 ,  H04L9/08 ,  G11C16/22 ,  H04L29/06

CPC classification number: G11C7/06 ,  G11C16/22 ,  H04L9/0841 ,  H04L9/3263 ,  H04L63/0823

Abstract: An electronic device includes a non-volatile memory having a plurality of memory cells, a memory controller, and an evaluator. The memory controller is configured to provide control signals to the non-volatile memory causing the non-volatile memory, or a selected memory section of the non-volatile memory, to be in one of a read state and a weak erase state, wherein the weak erase state causes the plurality of memory cells to maintain different states depending on different physical properties of the plurality of memory cells. The evaluator is configured to read out the plurality of memory cells and to provide a readout pattern during the read state, wherein the readout pattern that is provided after a preceding weak erase state corresponds to a physically unclonable function (PUF) response of the electronic device uniquely identifying the electronic device.

Abstract translation: 电子设备包括具有多个存储单元的非易失性存储器，存储器控制器和评估器。 存储器控制器被配置为向非易失性存储器提供控制信号，使得非易失性存储器或非易失性存储器的所选存储器部分处于读取状态和弱擦除状态之一，其中， 弱擦除状态导致多个存储单元根据多个存储单元的不同物理特性来维持不同的状态。 评估器被配置为读出多个存储器单元并且在读取状态期间提供读出模式，其中在先前的弱擦除状态之后提供的读出模式对应于电子设备的物理不可克隆功能（PUF）响应 唯一地识别电子设备。

公开(公告)号：US20130099289A1

公开(公告)日：2013-04-25

申请号：US13711404

申请日：2012-12-11

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC: H01L23/52

CPC classification number: H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract translation: 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

公开(公告)号：US10937469B2

公开(公告)日：2021-03-02

申请号：US16666425

申请日：2019-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C7/10 ,  G06F11/10 ,  G06F11/25 ,  G06F12/02 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/34 ,  H03M13/13 ,  G11C29/26

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

公开(公告)号：US10157095B2

公开(公告)日：2018-12-18

申请号：US15490950

申请日：2017-04-19

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Michael Gössel ,  Thomas Rabenalt ,  Thomas Kern

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  H03M13/29 ,  H03M13/13 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

公开(公告)号：US20180151244A1

公开(公告)日：2018-05-31

申请号：US15821871

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C29/02 ,  G11C7/06

CPC classification number: G11C29/025 ,  G11C7/06 ,  G11C29/12005 ,  G11C29/702 ,  G11C29/82 ,  G11C2029/1202 ,  G11C2029/4402

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a plurality of word lines, each word line coupled with one or more memory cells, a plurality of non-volatile marking memory cells, wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells, and a plurality of marking bit lines, each associated with marking memory cells, a plurality of marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

公开(公告)号：US20170308431A1

公开(公告)日：2017-10-26

申请号：US15490950

申请日：2017-04-19

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Michael Gössel ,  Thomas Rabenalt ,  Thomas Kern

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/13

CPC classification number: G06F11/1044 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/13 ,  H03M13/136 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2903 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2957

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

公开(公告)号：US09153293B2

公开(公告)日：2015-10-06

申请号：US13690299

申请日：2012-11-30

Applicant: Infineon Technologies AG

Inventor： Thomas Nirschl ,  Jan Otterstedt ,  Alexander Duch

IPC: G11C29/00 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C7/00 ,  G11C16/0425 ,  G11C16/3427 ,  G11C16/349

Abstract: A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted.

Abstract translation: 操作集成电路的方法包括确定至少一个存储器单元的至少一个特性并对至少一个存储单元进行操作，其中基于所确定的至少一个特征来确定至少一个附加存储器单元的干扰 调整。

公开(公告)号：US20150214163A1

公开(公告)日：2015-07-30

申请号：US14166930

申请日：2014-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thomas Kuenemund ,  Jan Otterstedt ,  Christoph Saas

IPC: H01L23/00 ,  G01R31/28

CPC classification number: H01L23/57 ,  G01R31/2884 ,  G06F21/87 ,  G06F21/88 ,  H01L22/34 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test signal circuit configured to supply a test signal to the semiconductor region, a determiner configured to determine a behavior of the semiconductor region in response to the test signal and a detector configured to detect a change of geometry of the semiconductor region based on the behavior and a reference behavior of the semiconductor region in response to the test signal.

Abstract translation: 根据一个实施例，描述了芯片，其包括晶体管电平，位于晶体管电平以下或之下的半导体区域，被配置为向半导体区域提供测试信号的测试信号电路，被配置为确定 响应于测试信号的半导体区域的行为以及被配置成基于测试信号的半导体区域的行为和参考行为来检测半导体区域的几何形状的变化的检测器。

公开(公告)号：US20150067447A1

公开(公告)日：2015-03-05

申请号：US14018811

申请日：2013-09-05

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Rainer Goettfert

IPC: G06F11/10

CPC classification number: H04L1/0057 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/03 ,  H03M13/098 ,  H03M13/1174 ,  H03M13/19 ,  H03M13/2906

Abstract: An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information.

Abstract translation: 一个实施例涉及一种用于数据处理的方法，包括读取数据，包括开销信息和有效载荷信息的数据，以及确定数据的每个部分的状态，其中状态是第一二进制状态，第二二进制状态， 和一个未定义的状态。 该方法还包括基于其位置并基于开销信息来解码具有未定义状态的数据的至少一部分。