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    MONOLITHICALLY INTEGRATED SYSTEM ON CHIP FOR SILICON PHOTONICS
    3.
    发明申请
    MONOLITHICALLY INTEGRATED SYSTEM ON CHIP FOR SILICON PHOTONICS 有权

    公开(公告)号：US20210049124A1

    公开(公告)日：2021-02-18

    申请号：US17088197

    申请日：2020-11-03

    Applicant: Inphi Corporation

    Inventor： Radhakrishnan L. NAGARAJAN ,  Chao XU

    IPC: G06F15/78 ,  G06F13/42 ,  G02B6/12 ,  H04L27/00 ,  G06F13/364 ,  G06F13/40 ,  H04L1/00 ,  H04L25/03

    Abstract: The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.

    HYBRID MEMORY BLADE
    8.
    发明申请
    HYBRID MEMORY BLADE 有权
    混合记忆刀片

    公开(公告)号：US20150103481A1

    公开(公告)日：2015-04-16

    申请号：US14576008

    申请日：2014-12-18

    Applicant: INPHI CORPORATION

    Inventor： Christopher HAYWOOD ,  Chao XU ,  Fouad G. TAMER

    IPC: H05K7/14 ,  H05K7/20

    CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

    Abstract translation: 本发明涉及服务器系统及其方法。 更具体地，本发明的实施例提供了服务器系统内的存储器控​​制器，其中存储器控制器可分离地连接到一个或多个处理器，多个易失性存储器模块和多个固态存储器模块。 该存储器控制器可以连接到其他类似配置的存储器控​​制器。 可以移除和/或更换易失性和固态存储器模块。 还有其它实施例。

    MONOLITHICALLY INTEGRATED SYSTEM ON CHIP FOR SILICON PHOTONICS
    9.
    发明申请
    MONOLITHICALLY INTEGRATED SYSTEM ON CHIP FOR SILICON PHOTONICS 审中-公开

    公开(公告)号：US20190354507A1

    公开(公告)日：2019-11-21

    申请号：US16529473

    申请日：2019-08-01

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. NAGARAJAN ,  Chao XU

    IPC: G06F15/78 ,  G06F13/40 ,  G06F13/42 ,  H04L25/03 ,  H04L1/00 ,  G02B6/12 ,  H04L27/00 ,  G06F13/364

    Abstract: The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.

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