公开(公告)号：US20190003888A1

公开(公告)日：2019-01-03

申请号：US15638829

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Abram M. Detofsky ,  Brett E. Klehn

IPC: G01J3/04 ,  G01J3/02 ,  G01J3/28 ,  G01J3/12

Abstract: An optical spectral analyzer for measuring an optical multi-channel signal by separating the multi-channel signal and measuring a plurality of single-channel signals simultaneously. The spectral analyzer can include a demultiplexer configured to receive the multi-channel signal. The multi-channel signal can be a multi-channel wavelength range. The demultiplexer can separate the multi-channel signal into the plurality of single-channel signals including a first single-channel signal and a second single-channel signal. The spectral analyzer can include a plurality of optical paths. The plurality of optical paths can include a plurality of respective detectors for measuring an optical power of the respective single-channel signals. The detectors can convert the optical power of the respective single-channel signals to corresponding electrical signals. In some examples, the spectral analyzer includes a controller configured to obtain the plurality of respective electrical signals simultaneously to correspondingly detect the optical power of the multi-channel signal across the multi-channel wavelength range.

公开(公告)号：US20180045759A1

公开(公告)日：2018-02-15

申请号：US15370870

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  Andrew J. Hoitink ,  Abram M. Detofsky ,  Joe F. Walczyk

IPC: G01R1/073 ,  G01B7/00 ,  G01R31/28

CPC classification number: G01R1/07328 ,  G01B7/003 ,  G01R1/06794 ,  G01R31/2891

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

公开(公告)号：US20180188288A1

公开(公告)日：2018-07-05

申请号：US15393640

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Erkan Acar ,  Abram M. Detofsky ,  Jin Pan

IPC: G01R1/04 ,  G01R31/28

Abstract: In one embodiment, a device to test one or more electronic components comprises a first card comprising a first test device communicatively coupled to at least a first connector assembly positioned on the first card and a second card comprising a second test device communicatively coupled to at least a second connector assembly positioned on the second card. The at least a first connector assembly is directly communicatively coupled to the at least a second connector assembly to provide a direct communication interface between the first test device and the second test device that is not routed via a backplane. Other embodiments may be described.

公开(公告)号：US12135460B2

公开(公告)日：2024-11-05

申请号：US17132912

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Todd R. Coons ,  Michael Rutigliano ,  Joe F. Walczyk ,  Abram M. Detofsky

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34 ,  H01L25/075 ,  H01L33/58 ,  H01L33/62 ,  H01L23/367 ,  H04B10/40

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.

公开(公告)号：US09869714B2

公开(公告)日：2018-01-16

申请号：US15185468

申请日：2016-06-17

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  James G. Maveety ,  Abram M. Detofsky ,  James E. Neeb

IPC: G01R31/00 ,  G01R31/28 ,  G01R1/44 ,  H05K7/20 ,  G01R1/067 ,  G01R31/26 ,  G01R1/04

CPC classification number: G01R31/2874 ,  G01R1/0458 ,  G01R1/06722 ,  G01R1/06783 ,  G01R1/44 ,  G01R31/2642 ,  G01R31/2875 ,  G01R31/2891 ,  H05K7/20

Abstract: A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target setpoint temperature based on the data and a dynamic thermal controller to receive the target setpoint temperature from the thermal control interface and control a thermal actuator based on the target setpoint temperature.

公开(公告)号：US12061230B2

公开(公告)日：2024-08-13

申请号：US17131604

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Todd R. Coons ,  Michael Rutigliano ,  Joe F. Walczyk ,  Abram M. Detofsky

IPC: G01R31/308 ,  G02B6/42

CPC classification number: G01R31/308 ,  G02B6/4256 ,  G02B6/4292

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical plugs used to cover optical connectors of a photonics package to protect the connectors. The active optical plugs may also be used to perform testing of the photonics package, including generating light to be sent to the photonics package and to detect light received from the photonics package as part of the test protocol. This allows testing the optical connection and the photonics package, without exposing the optical connections of the package to damage from dust or physical contact. Other embodiments may be described and/or claimed.

公开(公告)号：US10677845B2

公开(公告)日：2020-06-09

申请号：US15447095

申请日：2017-03-01

Applicant: Intel Corporation

Inventor： Abram M. Detofsky ,  Evan M. Fledell ,  Mustapha A. Abdulai ,  John M. Peterson ,  Dinia P. Kitendaugh ,  Pooya Tadayon ,  Jin Pan ,  David Shia

IPC: G01R31/319 ,  G01R31/28

Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

公开(公告)号：US10324112B2

公开(公告)日：2019-06-18

申请号：US15370870

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  Andrew J. Hoitink ,  Abram M. Detofsky ,  Joe F. Walczyk

IPC: G01R1/073 ,  G01B7/00 ,  G01R1/067 ,  G01R31/28

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

公开(公告)号：US10247773B2

公开(公告)日：2019-04-02

申请号：US15200997

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Sankaran M. Menon ,  Rehan M. Sheikh ,  Rolf H. Kuehnis ,  John Michael Peterson ,  Asifur Rahman ,  Abram M. Detofsky ,  Mohsen Fazlian

IPC: G01R31/28 ,  H04B1/40 ,  H04W4/00 ,  H04W88/06 ,  H04W4/80 ,  H04W24/06

Abstract: The disclosed systems, devices, and methods may provide for wireless testing of devices and, in particular, wireless testing of semiconductor devices comprising integrated circuits, memory, and logic circuitry that can be present on a wafer. The semiconductor devices can be tested for functional defects by applying one or more test patterns to the semiconductor devices. Further, for devices under test that do not have built-in wireless connectivity (for example, those that do not have a built-in Bluetooth low-energy engine), the disclosure describes systems and methods that the devices under test can use for external wireless connectivity (e.g., an external board having Bluetooth low-energy) on the low-bandwidth interface. In one example embodiment, for high-bandwidth scan testing, wireless connectivity modules (such as those implementing WiFi or WiGig) are described, which can be used to meet the bandwidth requirements of the one or more tests.

公开(公告)号：US08926196B2

公开(公告)日：2015-01-06

申请号：US13631619

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Abram M. Detofsky ,  Chukwunenye S. Nnebe ,  Jin Yang ,  Tak M. Mak ,  Sasha N. Oster

IPC: G02B6/36

CPC classification number: G02B6/423 ,  G02B6/4204

Abstract: Provided are a method and a system, in which a first device aligns a chip to a socket along a first axis. A second device aligns the chip to the socket along a second axis, and a third device aligns the chip to the socket along a plane formed by the first axis and a third axis. Also provided is a system comprising a first optical element, and a second optical element, where a first elastic element is coupled to the first optical element, and a second elastic element is coupled to the second optical element, and where the first elastic element is aligned to the second elastic element via elastic coupling.

Abstract translation: 提供了一种方法和系统，其中第一设备沿着第一轴将芯片对准插座。 第二装置沿着第二轴将芯片对准插座，并且第三装置沿着由第一轴线和第三轴线形成的平面将芯片对准插座。 还提供了一种包括第一光学元件和第二光学元件的系统，其中第一弹性元件联接到第一光学元件，并且第二弹性元件联接到第二光学元件，并且其中第一弹性元件是 通过弹性联轴器对准第二弹性元件。