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公开(公告)号：US20190286559A1
公开(公告)日：2019-09-19
申请号：US16433671
申请日：2019-06-06
Applicant: Intel Corporation
Inventor： Avinash Sodani , Robert J. Kyanko , Richard J. Greco , Andreas Kleen , Milind B. Girkar , Christopher M. Cantalupo
Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
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公开(公告)号：US09886396B2
公开(公告)日：2018-02-06
申请号：US14581285
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Roger Gramunt , Rammohan Padmanabhan , Ramon Matas , Neal S. Moyer , Benjamin C. Chaffin , Avinash Sodani , Alexey P. Suprun , Vikram S. Sundaram , Chung-Lun Chan , Gerardo A. Fernandez , Julio Gago , Michael S. Yang , Aditya Kesiraju
CPC classification number: G06F12/122 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3859 , G06F9/4806 , G06F2212/62
Abstract: In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.
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公开(公告)号：US09836399B2
公开(公告)日：2017-12-05
申请号：US14671411
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Krishna N. Vinod , Avinash Sodani , Zainulabedin Aurangabadwala
IPC: G06F12/12 , G06F12/0831 , G06F12/0811 , G06F12/123 , G06F12/0804
CPC classification number: G06F12/0833 , G06F12/0804 , G06F12/0811 , G06F12/123 , G06F2212/1008
Abstract: A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status.
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公开(公告)号：US09733939B2
公开(公告)日：2017-08-15
申请号：US13631664
申请日：2012-09-28
Applicant: Intel Corporation
Inventor： Vijaykumar Balaram Kadgi , James D. Hadley , Avinash Sodani , Matthew C. Merten , Morris Marden , Joseph A. McMahon , Grace C. Lee , Laura A. Knauth , Robert S. Chappell , Fariborz Tabesh
CPC classification number: G06F9/30105 , G06F9/384
Abstract: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.
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5.发明授权Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources 有权基于对数据源的内存访问计数的预取器调节的指令和逻辑公开(公告)号：US09507596B2
公开(公告)日：2016-11-29
申请号：US14471261
申请日：2014-08-28
Applicant: Intel Corporation
Inventor： Ashok Jagannathan , Prabhat Jain , Krishna N. Vinod , Avinash Sodani
CPC classification number: G06F9/30047 , G06F9/383 , G06F9/3887 , G06F12/0646 , G06F12/0862 , G06F2212/6026 , G06F2212/6028
Abstract: A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.
Abstract translation: 处理器包括核心，预取器和预取器控制模块。 预取器包括通过内存子系统进行推测预取请求的逻辑，用于由核心执行的元素，以及将预取元素存储在高速缓存中的逻辑。 预取器控制模块包括用于确定对两种类型的存储器的存储器访问的计数的逻辑，并且基于计数和存储器的类型，减少预取器的推测性预取请求。
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Patent Agency Ranking
公开(公告)号：US20160062768A1
公开(公告)日：2016-03-03
申请号：US14471261
申请日：2014-08-28
Applicant: Intel Corporation
Inventor： Ashok Jagannathan , Prabhat Jain , Krishna N. Vinod , Avinash Sodani
CPC classification number: G06F9/30047 , G06F9/383 , G06F9/3887 , G06F12/0646 , G06F12/0862 , G06F2212/6026 , G06F2212/6028
Abstract: A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.
Abstract translation: 处理器包括核心，预取器和预取器控制模块。 预取器包括用于通过存储器子系统进行推测预取请求的逻辑，用于由核心执行的元素以及将预取元素存储在高速缓存中的逻辑。 预取器控制模块包括用于确定对两种类型的存储器的存储器访问的计数的逻辑，并且基于计数和存储器的类型，减少预取器的推测性预取请求。
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公开(公告)号：US20170357580A1
公开(公告)日：2017-12-14
申请号：US15628811
申请日：2017-06-21
Applicant: Intel Corporation
Inventor： Avinash Sodani , Robert J. Kyanko , Richard J. Greco , Andreas Kleen , Milind B. Girkar , Christopher M. Cantalupo
CPC classification number: G06F12/0646 , G06F12/023 , G06F2212/283
Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
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公开(公告)号：US20160224252A1
公开(公告)日：2016-08-04
申请号：US14609904
申请日：2015-01-30
Applicant: Intel Corporation
Inventor： Steven R. Hutsell , Rajat Agarwal , Avinash Sodani , Darrell S. McGinnis
CPC classification number: G06F12/0802 , G06F12/0895 , G06F2212/225
Abstract: Hybrid memory architecture technologies are described. In accordance with embodiments disclosed herein, there is provided a processing device having a core and a memory controller communicably coupled to the core to receive a request to fetch data. The memory controller is communicably coupled to a hybrid memory architecture including a near memory, wherein the near memory is divided into a flat memory region and a cache memory region.
Abstract translation: 描述了混合存储器架构技术。 根据本文公开的实施例，提供了一种处理设备，其具有核心和可通信地耦合到核心的存储器控制器，以接收获取数据的请求。 存储器控制器可通信地耦合到包括近存储器的混合存储器架构，其中近端存储器被划分为平坦存储器区域和高速缓冲存储器区域。
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公开(公告)号：US11526440B2
公开(公告)日：2022-12-13
申请号：US16433671
申请日：2019-06-06
Applicant: Intel Corporation
Inventor： Avinash Sodani , Robert J. Kyanko , Richard J. Greco , Andreas Kleen , Milind B. Girkar , Christopher M. Cantalupo
Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
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公开(公告)号：US20170161106A1
公开(公告)日：2017-06-08
申请号：US15385823
申请日：2016-12-20
Applicant: Intel Corporation
Inventor： Morris Marden , Matthew Merten , Alexandre Farcy , Avinash Sodani , James Hadley , Ilhyun Kim
CPC classification number: G06F9/50 , G06F9/30101 , G06F9/3851 , G06F2209/5014
Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.
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