公开(公告)号：US20150270224A1

公开(公告)日：2015-09-24

申请号：US14675613

申请日：2015-03-31

Applicant: Intel Corporation

Inventor： Boyan BOYANOV ,  Kanwal Jit SINGH

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract translation: 在衬底上的电介质层中的至少一个导电线凹入以形成沟道。 通道与导线自对准。 可以通过使用包含抑制剂的化学品将导电线蚀刻到预定深度来形成沟道，以提供独立于晶体取向的蚀刻均匀性。 用于防止电迁移的覆盖层沉积在通道中的凹进的导电线上。 通道被配置为在导电线的宽度内容纳覆盖层。

公开(公告)号：US20140239345A1

公开(公告)日：2014-08-28

申请号：US14268938

申请日：2014-05-02

Applicant: INTEL CORPORATION

Inventor： Boyan BOYANOV ,  Anand S. MURTHY ,  Brian S. DOYLE ,  Robert S. CHAU

IPC: H01L29/78 ,  H01L27/092

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract translation: 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

公开(公告)号：US20160336447A1

公开(公告)日：2016-11-17

申请号：US15220355

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Anand MURTHY ,  Boyan BOYANOV ,  Glenn A. GLASS ,  Thomas HOFFMAN

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L29/06 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/36 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US20200321282A1

公开(公告)日：2020-10-08

申请号：US16908478

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Boyan BOYANOV ,  Kanwal Jit SINGH

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US20190393157A1

公开(公告)日：2019-12-26

申请号：US16559086

申请日：2019-09-03

Applicant: Intel Corporation

Inventor： Boyan BOYANOV ,  Kanwal Jit SINGH

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.