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公开(公告)号：US11327861B2
公开(公告)日：2022-05-10
申请号：US17106946
申请日：2020-11-30
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
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公开(公告)号：US11288154B2
公开(公告)日：2022-03-29
申请号：US17114089
申请日：2020-12-07
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
IPC: G06F11/30 , H04L12/26 , H04L1/20 , H04L12/933 , H04L29/06 , H04L29/08 , H04L43/0823 , H04L49/10 , H04L69/00 , H04L69/323 , H04L43/10 , H04L1/18
Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.
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公开(公告)号：US10671476B2
公开(公告)日：2020-06-02
申请号：US15761405
申请日：2015-09-26
Applicant: Intel Corporation , Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
Inventor： Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.
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公开(公告)号：US12135581B2
公开(公告)日：2024-11-05
申请号：US17955234
申请日：2022-09-28
Applicant: Intel Corporation
Inventor： David J. Harriman , Debendra Das Sharma , Daniel S. Froelich , Sean O. Stalley
IPC: G06F1/14 , G06F13/42 , H04B1/7073 , H04L69/14
Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
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公开(公告)号：US20230022948A1
公开(公告)日：2023-01-26
申请号：US17955234
申请日：2022-09-28
Applicant: Intel Corporation
Inventor： David J. Harriman , Debendra Das Sharma , Daniel S. Froelich , Sean O. Stalley
IPC: G06F1/14 , G06F13/42 , H04B1/7073
Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
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Patent Agency Ranking
公开(公告)号：US20160179710A1
公开(公告)日：2016-06-23
申请号：US14580918
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich , Venkatraman Iyer , Michelle C. Jen , Rahul R. Shah , Eric M. Lee
CPC classification number: G06F13/4068 , G06F13/1642 , G06F13/1673 , G06F13/385 , G06F13/4282
Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.
Abstract translation: 提供了一种包括用于串行互连的物理接口的装置。 物理接口包括缓冲器，其可选择用作缓冲器控制线上的电压电平的漂移缓冲器或弹性缓冲器。 物理接口还包括可由逻辑控制线上的电压电平启用或禁用的编码逻辑。 此外，物理接口还包括可以通过通信控制线上的电压电平启用或禁用的有序集发生器。
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公开(公告)号：US20160124894A1
公开(公告)日：2016-05-05
申请号：US14991293
申请日：2016-01-08
Applicant: Intel Corporation
Inventor： David J. Harriman , Mahesh Wagh , Abdul R. Ismail , Daniel S. Froelich
CPC classification number: G06F13/4282 , G06F1/14 , G06F13/00 , G06F13/385 , H04L43/0858 , H04L43/106
Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.
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公开(公告)号：US10860449B2
公开(公告)日：2020-12-08
申请号：US15476571
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Daniel S. Froelich
Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.
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公开(公告)号：US10534034B2
公开(公告)日：2020-01-14
申请号：US15039515
申请日：2013-12-26
Applicant: Intel Corporation
Inventor： Daniel S. Froelich , Debendra Das Sharma
IPC: G01R31/317 , H04B3/46 , G06F11/22 , G01R31/3177 , G06F11/36 , H01L21/66 , G06F11/00 , G06F13/16 , G01R31/28 , G01R31/327 , G06F11/07
Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.
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公开(公告)号：US20190041898A1
公开(公告)日：2019-02-07
申请号：US15920249
申请日：2018-03-13
Applicant: Intel Corporation
Inventor： David J. Harriman , Debendra Das Sharma , Daniel S. Froelich , Sean O. Stalley
IPC: G06F1/14 , G06F13/42 , H04B1/7073
Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
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