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    Method, apparatus, and system for measurement of noise statistics and bit error ratio estimation
    1.
    发明授权
    Method, apparatus, and system for measurement of noise statistics and bit error ratio estimation 有权
    用于测量噪声统计和误码率估计的方法，装置和系统

    公开(公告)号：US09374202B2

    公开(公告)日：2016-06-21

    申请号：US13842320

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Adee O. Ran ,  Amir Mezer ,  Ophir Gazinski ,  Sanjay R. Ravi ,  David G. Ellis ,  Stephen J. Peters ,  Jeffrey M. Shuey

    IPC: G06F11/00 ,  G01R19/00 ,  H04L1/00 ,  H04L1/20

    CPC classification number: H04L1/203

    Abstract: A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ratio determined for a device.

    Abstract translation: 从第一限幅元件和第二限幅元件的装置接收采样电压。 基于样本电压确定第一限幅元件的判定，并根据采样电压与第二限幅元件的判定进行比较。 第二限幅元件的决定是从采样电压与第二限幅元件的参考电压的比较产生的。 比较决策可以是为设备确定的软错误率的基础。

    Training for chip select signal read operations by memory devices
    5.
    发明授权
    Training for chip select signal read operations by memory devices 有权

    公开(公告)号：US12009023B2

    公开(公告)日：2024-06-11

    申请号：US17441667

    申请日：2019-05-24

    Applicant: Intel Corporation

    Inventor： Zhenglong Wu ,  Tonia G. Morris ,  Christina Jue ,  Daniel Becerra Perez ,  David G. Ellis

    IPC: G11C11/4076 ,  G11C11/4096

    CPC classification number: G11C11/4076 ,  G11C11/4096

    Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

    Memory subsystem data bus stress testing
    6.
    发明授权
    Memory subsystem data bus stress testing 有权
    内存子系统数据总线压力测试

    公开(公告)号：US09009531B2

    公开(公告)日：2015-04-14

    申请号：US13706177

    申请日：2012-12-05

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi ,  David G. Ellis

    IPC: G06F11/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/36 ,  G11C29/50 ,  G11C29/52

    CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/06 ,  G11C29/36 ,  G11C29/50012 ,  G11C29/52

    Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

    Abstract translation: 存储器子系统包括存储器控制器的测试信号发生器，其响应于存储器控制器接收测试事务而产生测试数据信号。 测试事务指示在相关联的存储设备上执行的一个或多个I / O操作。 测试信号发生器可以从各种不同的模式发生器产生数据信号。 存储器控制器调度器调度测试数据信号模式，并将其发送到存储器件。 然后，存储器件可以执行I / O操作来实现测试事务。 存储器控制器可以读取写入存储器件的特定地址的数据，并将回读数据与预期数据进行比较。 当回读数据和预期数据不匹配时，存储器控制器可以记录错误。 该错误可以包括错误的具体地址，特定数据和/或编码数据。

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