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    Interface for storage device access over memory bus
    2.
    发明授权
    Interface for storage device access over memory bus 有权

    公开(公告)号：US10025737B2

    公开(公告)日：2018-07-17

    申请号：US14731183

    申请日：2015-06-04

    Applicant: Intel Corporation

    Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC: G06F13/28 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G06F1/12 ,  G06F13/40 ,  G06F13/38 ,  H04L5/00 ,  H04L7/00

    Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    Boundary scan chain for stacked memory
    4.
    发明授权
    Boundary scan chain for stacked memory 有权
    用于堆叠内存的边界扫描链

    公开(公告)号：US09476940B2

    公开(公告)日：2016-10-25

    申请号：US14145478

    申请日：2013-12-31

    Applicant: Intel Corporation

    Inventor： David J. Zimmerman

    IPC: G11C5/04 ,  G11C29/32 ,  G01R31/3185 ,  G01R31/3177

    CPC classification number: G11C29/32 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/318572 ,  G11C5/04 ,  G11C11/4087 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

    Abstract translation: 堆叠式存储器的边界扫描链。 存储器件的实施例包括系统元件和包括一个或多个存储管芯层的存储器堆叠，每个存储器管芯层包括用于I / O单元的输入输出（I / O）单元和边界扫描链。 存储芯片层的边界扫描链包括用于每个I / O单元的扫描链部分，用于I / O单元的扫描链部分包括第一扫描逻辑多路复用器，扫描逻辑锁存器，扫描逻辑的输入 锁存器与第一扫描逻辑多路复用器的输出耦合，以及解码器，用于向边界扫描链提供命令信号。

    Write data mask for power reduction
    5.
    发明授权
    Write data mask for power reduction 有权

    公开(公告)号：US10541009B2

    公开(公告)日：2020-01-21

    申请号：US15857349

    申请日：2017-12-28

    Applicant: Intel Corporation

    Inventor： David J. Zimmerman ,  Robert M. Ellis ,  Rajesh Sundaram

    IPC: G06F3/06 ,  G11C7/10

    Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.

    Boundary scan chain for stacked memory
    6.
    发明授权
    Boundary scan chain for stacked memory 有权

    公开(公告)号：US10347354B2

    公开(公告)日：2019-07-09

    申请号：US15293123

    申请日：2016-10-13

    Applicant: Intel Corporation

    Inventor： David J. Zimmerman

    IPC: G11C5/04 ,  G11C29/32 ,  G11C11/408 ,  G01R31/3177 ,  G01R31/3185

    Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

    Interface for storage device access over memory bus
    10.
    发明授权
    Interface for storage device access over memory bus 有权
    通过存储器总线访问存储设备的接口

    公开(公告)号：US09064560B2

    公开(公告)日：2015-06-23

    申请号：US14075765

    申请日：2013-11-08

    Applicant: Intel Corporation

    Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F13/16 ,  G11C7/22

    CPC classification number: G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    Abstract translation: 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

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