公开(公告)号：US10756931B2

公开(公告)日：2020-08-25

申请号：US16452381

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Tawfiq Musah ,  Hariprasath Venkatram ,  Bryan K. Casper

IPC: H04L25/03 ,  H04L7/033 ,  H04L7/00

Abstract: Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

公开(公告)号：US09537682B2

公开(公告)日：2017-01-03

申请号：US14660799

申请日：2015-03-17

Applicant: Intel Corporation

Inventor： Hariprasath Venkatram ,  Sami Hyvonen ,  Tawfiq Musah ,  Bryan K. Casper

IPC: H04B1/18 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L25/03057 ,  H04L7/0062 ,  H04L7/033 ,  H04L7/0334 ,  H04L25/03878

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract translation: 描述了一种装置，包括：放大器; 第一组采样器，用于根据时钟信号对从放大器输出的数据进行采样，该采样器组用于产生输出; 以及将第一组采样器的输出转换为1 -hot编码数据的转换器。

公开(公告)号：US20190312756A1

公开(公告)日：2019-10-10

申请号：US16452381

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Tawfiq Musah ,  Hariprasath Venkatram ,  Bryan K. Casper

IPC: H04L25/03 ,  H04L7/033

Abstract: Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

公开(公告)号：US10923164B2

公开(公告)日：2021-02-16

申请号：US16147634

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Hariprasath Venkatram ,  Mohammed G. Mostofa ,  Rajesh Inti ,  Roger K. Cheng ,  Aaron Martin ,  Christopher Mozak ,  Pavan Kumar Kappagantula ,  Hsien-Pao Yang ,  Mozhgan Mansuri ,  James Jaussi ,  Harishankar Sridharan

IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/16

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

公开(公告)号：US10341145B2

公开(公告)日：2019-07-02

申请号：US14637291

申请日：2015-03-03

Applicant: Intel Corporation

Inventor： Tawfiq Musah ,  Hariprasath Venkatram ,  Bryan K. Casper

IPC: H04L7/00 ,  H04L25/03 ,  H04L7/033

Abstract: Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

公开(公告)号：US20160277219A1

公开(公告)日：2016-09-22

申请号：US14660799

申请日：2015-03-17

Applicant: Intel Corporation

Inventor： Hariprasath Venkatram ,  Sami Hyvonen ,  Tawfiq Musah ,  Bryan K. Casper

IPC: H04L25/03 ,  H04L7/033

CPC classification number: H04L25/03057 ,  H04L7/0062 ,  H04L7/033 ,  H04L7/0334 ,  H04L25/03878

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract translation: 描述了一种装置，包括：放大器; 第一组采样器，用于根据时钟信号对从放大器输出的数据进行采样，该采样器组用于产生输出; 以及将第一组采样器的输出转换为1 -hot编码数据的转换器。

公开(公告)号：US20160261435A1

公开(公告)日：2016-09-08

申请号：US14637291

申请日：2015-03-03

Applicant: INTEL CORPORATION

Inventor： Tawfiq Musah ,  Hariprasath Venkatram ,  Bryan K. Casper

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L7/0062 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Abstract translation: 描述了一种装置，其包括：可变增益放大器（VGA）; 一组采样器，用于根据时钟信号对从VGA输出的数据进行采样; 以及时钟数据恢复（CDR）电路，用于调整时钟信号的相位，使得与采样数据相关联的第一后置光标信号的大小基本上是与采样数据相关联的主光标抽头的幅度的一半。