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公开(公告)号：US11374164B2
公开(公告)日：2022-06-28
申请号：US16024714
申请日：2018-06-29
申请人： Intel Corporation
发明人： Tanay Gosavi , Sasikanth Manipatruni , Chia-Ching Lin , Kaan Oguz , Christopher Wiegand , Angeline Smith , Noriyuki Sato , Kevin O'Brien , Benjamin Buford , Ian Young , Md Tofizur Rahman
摘要： Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.
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公开(公告)号：US11031545B2
公开(公告)日：2021-06-08
申请号：US16327603
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： Kaan Oguz , Kevin P. O'Brien , Brian S. Doyle , Mark L. Doczy , Charles C. Kuo , Daniel G. Ouellette , Christopher J. Wiegand , Md Tofizur Rahman , Brian Maertz
摘要： Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.
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公开(公告)号：US10559744B2
公开(公告)日：2020-02-11
申请号：US16072301
申请日：2016-04-01
申请人： Intel Corporation
发明人： Brian Maertz , Christopher J. Wiegand , Daniel G. Oeullette , Md Tofizur Rahman , Oleg Golonzka , Justin S. Brockman , Tahir Ghani , Brian S. Doyle , Kevin P. O'Brien , Mark L. Doczy , Kaan Oguz
摘要： An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
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公开(公告)号：US10079266B2
公开(公告)日：2018-09-18
申请号：US15122129
申请日：2014-03-28
申请人： Intel Corporation
发明人： Christopher J. Wiegand , Md Tofizur Rahman , Oleg Golonzka , Anant H. Jahagirdar , Mengcheng Lu
CPC分类号： H01L27/222 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.
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