公开(公告)号：US20230197728A1

公开(公告)日：2023-06-22

申请号：US17554791

申请日：2021-12-17

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Eric Mattson ,  Sudarat Lee ,  Sarah Atanasov ,  Christopher J. Jezewski ,  Charles Mokhtarzadeh ,  Thoe Michaelos ,  I-Cheng Tung ,  Charles C. Kuo ,  Scott B. Clendenning ,  Matthew V. Metz

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

摘要： An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.

公开(公告)号：US20200043536A1

公开(公告)日：2020-02-06

申请号：US15735625

申请日：2015-06-26

申请人： Intel Corporation

发明人： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： An embodiment includes an apparatus comprising: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, comprising a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.

公开(公告)号：US10395707B2

公开(公告)日：2019-08-27

申请号：US15503359

申请日：2014-09-26

申请人： Intel Corporation

发明人： Mark L. Doczy ,  Kaan Oguz ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau ,  Satyarth Suri

IPC分类号： H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01L27/22

摘要： A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20190221734A1

公开(公告)日：2019-07-18

申请号：US16327603

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Daniel G. Ouellette ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian Maertz

IPC分类号： H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

摘要： Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

公开(公告)号：US20190115353A1

公开(公告)日：2019-04-18

申请号：US16082261

申请日：2016-04-01

申请人： Intel Corporation

发明人： Kevin P. O'Brien ,  Brian S. Doyle ,  Kaan Oguz ,  Charles C. Kuo ,  Mark L. Doczy ,  Tejaswi K. Indukuri

IPC分类号： H01L27/1159 ,  H01L27/11587 ,  H01L29/78 ,  G11C11/22

摘要： A monocrystalline metal-oxide stack including a ferroelectric (FE) tunneling layer and a buffer layer is epitaxially grown on a growth substrate. A first polycrystalline metal electrode layer is deposited over the tunneling layer. A bonding material layer is further deposited over the electrode layer. The bonding material layer is then bonded to a material layer on a front or back side of a host substrate that further comprises a transistor cell. Once bonded, the growth substrate may be removed from the metal-oxide stack to complete a transfer of the metal-oxide stack from the growth substrate to the host substrate. A second polycrystalline metal electrode layer is then deposited over the exposed buffer layer, placing both electrodes in close proximity to the FE tunneling layer.

公开(公告)号：US09825095B2

公开(公告)日：2017-11-21

申请号：US15247710

申请日：2016-08-25

申请人： INTEL CORPORATION

发明人： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

IPC分类号： H01L27/24 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00

CPC分类号： H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

摘要： An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

公开(公告)号：US09818864B2

公开(公告)日：2017-11-14

申请号：US15040978

申请日：2016-02-10

申请人： Intel Corporation

发明人： Brian S. Doyle ,  Roza Kotlyar ,  Uday Shah ,  Charles C. Kuo

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/165 ,  H01L29/16

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

摘要： Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

公开(公告)号：US20170323928A1

公开(公告)日：2017-11-09

申请号：US15658078

申请日：2017-07-24

申请人： INTEL CORPORATION

发明人： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Dmitri E. Nikonov ,  Robert S. Chau

IPC分类号： H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  G11C19/00

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/08

摘要： The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.

公开(公告)号：US09812574B2

公开(公告)日：2017-11-07

申请号：US14938739

申请日：2015-11-11

申请人： INTEL CORPORATION

发明人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  G11C11/412 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

摘要： Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006499A1

公开(公告)日：2024-01-04

申请号：US17854242

申请日：2022-06-30

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Kai Loon Cheong ,  Pooja Nath ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Charles C. Kuo ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Thoe Michaelos ,  David Kohen

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/78696 ,  H01L29/6681

摘要： An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.