公开(公告)号：US10372647B2

公开(公告)日：2019-08-06

申请号：US14977773

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Thomas D. Lovett ,  Michael A. Parker ,  Mark S. Birrittella

IPC: G06F13/00 ,  G06F13/40 ,  G06F1/12 ,  G06F13/364 ,  G06F13/42

Abstract: Methods and apparatus for implementing time synchronization across exascale fabrics. A master clock node is coupled to a plurality of slave nodes via a fabric comprising a plurality of fabric switches and a plurality of fabric links, wherein each slave node is connected to the master clock node via a respective clock tree path that traverses at least one fabric switch. The fabric switches are configured to selectively forward master clock time data internally along paths with fixed latencies that bypass the switches' buffers and switch circuitry, which enables the entire clock tree paths to also have fixed latencies. The fixed latency of the clock tree path is determined for each slave node. The local clocks of the slave nodes are then synchronized with the master clock by using master clock time data received by each slave node and the fixed latency of the clock tree path from the master clock node to the slave node that is determined. Techniques for determining a clock rate mismatch between the master clock and a local clock is also provided.

公开(公告)号：US10326711B2

公开(公告)日：2019-06-18

申请号：US15531643

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker ,  Steven F. Hoover ,  Gregory J. Hubbard

IPC: H04L12/933 ,  H04L12/937

Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.

公开(公告)号：US20190097935A1

公开(公告)日：2019-03-28

申请号：US15716831

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  Eric R. Borch ,  Timo Schneider ,  Michael A. Parker

IPC: H04L12/815 ,  H04L12/26 ,  H04L12/721

Abstract: Technologies for improving throughput in a network include a node switch. The node switch is to obtain expected performance data indicative of an expected data transfer performance of the node switch. The node switch is also to obtain measured performance data indicative of a measured data transfer performance of the node switch, compare the measured performance data to the expected performance data to determine whether the measured data transfer performance satisfies the expected data transfer performance, determine, as a function of whether the measured data transfer performance satisfies the expected data transfer performance, whether to force a unit of data through a non-minimal path to a destination, and send, in response to a determination to force the unit of data to be sent through a non-minimal path, the unit of data to an output port of the node switch associated with the non-minimal path. Other embodiments are also described.

公开(公告)号：US11528229B2

公开(公告)日：2022-12-13

申请号：US16929064

申请日：2020-07-14

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

IPC: H04L47/24 ,  H04L47/2425 ,  H04L49/356 ,  H04L47/70 ,  H04L43/0894 ,  H04L45/64 ,  H04L47/283

Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

公开(公告)号：US10333848B2

公开(公告)日：2019-06-25

申请号：US15200453

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  Eric R. Borch ,  Michael A. Parker ,  Scott S. Diesing

IPC: H04L12/801 ,  H04L12/26 ,  H04L12/835 ,  H04L12/935

Abstract: Technologies for adaptive routing using throughput estimation that includes a network switch. The network switch is configured to determine an adjusted average saturation count for each output buffer queue as a function of a present value of a saturation counter of a corresponding output buffer queue and a weighted average saturation count and a running average saturation count for each of the plurality of output buffer queues as a function of the corresponding captured present value and the adjusted average saturation count. The network switch is further configured to determine a congestion rate value for each output buffer queue and a total congestion value as a function of the congestion rate values and a standard occupancy congestion corresponding to a respective one of the plurality of output buffer queues. Other embodiments are described herein.

公开(公告)号：US10250524B2

公开(公告)日：2019-04-02

申请号：US15274715

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： Mario Flajslik ,  Gene Wu ,  Michael A. Parker

IPC: H04L12/24 ,  H04L12/927 ,  G06F15/16 ,  H04L12/741

Abstract: Technologies for increasing the bandwidth of partitioned hierarchical networks is disclosed. If each partition of network groups of a computer network are isolated, then the connections between the network groups of different partitions may go unused. However, careful selection of the network connections between partitions of different network groups may allow for a pseudo-direct connection between two network groups of the same partition using a single non-blocking switch in a network group of a different partition. Such a configuration can increase the effective bandwidth available within a partition without affecting the bandwidth available in another partition.

公开(公告)号：US20190044864A1

公开(公告)日：2019-02-07

申请号：US15859390

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Gary Muntz ,  Robert Zak ,  Thomas Lovett ,  Michael A. Parker

IPC: H04L12/803 ,  H04L12/66 ,  H04L12/801 ,  H04L12/851 ,  H04L12/825

Abstract: Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.

公开(公告)号：US20180351812A1

公开(公告)日：2018-12-06

申请号：US15941918

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Eric R. Borch ,  Robert C. Zak ,  Mario Flajslik ,  Jonathan M. Eastep ,  Michael A. Parker

IPC: H04L12/24 ,  H04L12/26

Abstract: Technologies for dynamic bandwidth management of interconnect fabric include a compute device configured to calculate a predicted fabric bandwidth demand which is expected to be used by the interconnect fabric in a next epoch and subsequent to a present epoch. The compute device is additionally configured to determine whether any global links and/or local links of the interconnect fabric can be disabled during the next epoch as a function of the calculated predicted fabric bandwidth demand and a number of redundant paths associated with the links of the interconnect fabric. The compute device is further configured to disable one or more of the global links and/or the local links that can be disabled, the one or more local links of the plurality of local links that can be disabled. Other embodiments are described herein.

公开(公告)号：US20220141138A1

公开(公告)日：2022-05-05

申请号：US17499949

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Vignesh Trichy Ravi ,  Ravi Murty ,  Ravindra Babu Ganapathi ,  Michael A. Parker

IPC: H04L47/12 ,  H04L47/11 ,  H04L47/30 ,  H04L47/2425 ,  H04L47/2483 ,  H04L47/263

Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.

公开(公告)号：US10771404B2

公开(公告)日：2020-09-08

申请号：US15388604

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： David Keppel ,  Thomas D. Lovett ,  Michael A. Parker ,  Robert C. Zak, Jr.

IPC: H04L12/879 ,  H04L12/26

Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request message, wherein the request message includes a read trigger, an indicator selector, and a completion trigger, determine an indicator that relates to the indicator selector, and perform an action when the read trigger is activated.