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公开(公告)号：US20220209778A1
公开(公告)日：2022-06-30
申请号：US17698844
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： Kuan-Yueh Shen , Nasser A. Kurd , John Fallin
Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
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公开(公告)号：US10854249B2
公开(公告)日：2020-12-01
申请号：US16914310
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US10790832B2
公开(公告)日：2020-09-29
申请号：US15933235
申请日：2018-03-22
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号：US11183226B2
公开(公告)日：2021-11-23
申请号：US17107704
申请日：2020-11-30
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US10706900B2
公开(公告)日：2020-07-07
申请号：US16178346
申请日：2018-11-01
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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Patent Agency Ranking
公开(公告)号：US20200004286A1
公开(公告)日：2020-01-02
申请号：US16566368
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , H03L7/093 , H03K5/24 , G01R19/165
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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公开(公告)号：US20180284828A1
公开(公告)日：2018-10-04
申请号：US15478457
申请日：2017-04-04
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , H03L7/093 , H03K5/24 , G01R19/165
CPC classification number: G05F1/625 , G01R19/16552 , H03K5/24 , H03L7/06
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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公开(公告)号：US12009827B2
公开(公告)日：2024-06-11
申请号：US17698844
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： Kuan-Yueh Shen , Nasser A. Kurd , John Fallin
CPC classification number: H03L7/0992 , H01R13/665 , H03L7/0893 , H03L7/189 , H01R2201/06
Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
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9.发明授权公开(公告)号：US11537375B2
公开(公告)日：2022-12-27
申请号：US16550134
申请日：2019-08-23
Applicant: Intel Corporation
Inventor： Julien Sebot , Edward A. Burton , Nasser A. Kurd , Jonathan Douglas
Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.
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公开(公告)号：US11442492B2
公开(公告)日：2022-09-13
申请号：US16292204
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： Mohamed A. Abdelmoneum , Nasser A. Kurd , Thripthi Hegde
Abstract: An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.
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