公开(公告)号：US20240113161A1

公开(公告)日：2024-04-04

申请号：US18540544

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Nicholas G. MINUTILLO ,  Sean T. MA ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/785

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20210091181A1

公开(公告)日：2021-03-25

申请号：US16580941

申请日：2019-09-24

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/78

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20240014268A1

公开(公告)日：2024-01-11

申请号：US18370586

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66439

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20200312958A1

公开(公告)日：2020-10-01

申请号：US16367134

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Anand MURTHY ,  Ryan KEECH ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/00

Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20220028972A1

公开(公告)日：2022-01-27

申请号：US17493695

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Nicholas G. MINUTILLO ,  Sean T. MA ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20190267289A1

公开(公告)日：2019-08-29

申请号：US16320425

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Sean T. MA ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Anand S. MURTHY ,  Harold W. KENNEL ,  Nicholas G. MINUTILLO ,  Jack T. KAVALIEROS ,  Willy RACHMADY

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.