公开(公告)号：US20220109072A1

公开(公告)日：2022-04-07

申请号：US17546002

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY ,  Harold W. KENNEL ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Glenn A. GLASS ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/165

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20240164080A1

公开(公告)日：2024-05-16

申请号：US18375858

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Peng ZHENG ,  Varun MISHRA ,  Harold W. KENNEL ,  Eric A. KARL ,  Tahir GHANI

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/10

CPC classification number: H10B10/12 ,  H01L29/0669 ,  H01L29/1037

Abstract: Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.

公开(公告)号：US20170162653A1

公开(公告)日：2017-06-08

申请号：US15433441

申请日：2017-02-15

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Harold W. KENNEL

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

Abstract: Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

公开(公告)号：US20220416050A1

公开(公告)日：2022-12-29

申请号：US17359327

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Cory BOMBERGER ,  Gilbert DEWEY ,  Anand S. MURTHY ,  Mauro KOBRINSKY ,  Rushabh SHAH ,  Chi-Hing CHOI ,  Harold W. KENNEL ,  Omair SAADAT ,  Adedapo A. ONI ,  Nazila HARATIPOUR ,  Tahir GHANI

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

公开(公告)号：US20200083354A1

公开(公告)日：2020-03-12

申请号：US16465763

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Van H. LE ,  Benjamin CHU-KUNG ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200066855A1

公开(公告)日：2020-02-27

申请号：US16074373

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Glenn A. GLASS ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Willy RACHMADY ,  Gilbert DEWEY ,  Sean T. MA ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/201

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

公开(公告)号：US20190267289A1

公开(公告)日：2019-08-29

申请号：US16320425

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Sean T. MA ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Anand S. MURTHY ,  Harold W. KENNEL ,  Nicholas G. MINUTILLO ,  Jack T. KAVALIEROS ,  Willy RACHMADY

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.

公开(公告)号：US20230420456A1

公开(公告)日：2023-12-28

申请号：US17850782

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Imola ZIGONEANU ,  Gilbert DEWEY ,  Anant H. JAHAGIRDAR ,  Harold W. KENNEL ,  Pratik PATEL ,  Anand S. MURTHY ,  Chi-Hing CHOI ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/161 ,  H01L29/167

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.

公开(公告)号：US20220310600A1

公开(公告)日：2022-09-29

申请号：US17842450

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Harold W. KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L21/8258 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：US20200066843A1

公开(公告)日：2020-02-27

申请号：US16612259

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Cheng-Ying HUANG ,  Harold W. KENNEL ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.