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    POOLING OF NETWORK PROCESSING RESOURCES
    2.
    发明申请
    POOLING OF NETWORK PROCESSING RESOURCES 有权

    公开(公告)号：US20210266253A1

    公开(公告)日：2021-08-26

    申请号：US17239329

    申请日：2021-04-23

    Applicant: Intel Corporation

    Inventor： Shaopeng HE ,  Haitao KANG ,  Cunming LIANG ,  Anjali Singhai JAIN ,  Parthasarathy SARANGAM ,  Yadong LI

    IPC: H04L12/721 ,  H04L12/741 ,  H04L12/707 ,  H04L12/803 ,  H04L29/06 ,  H04L12/46

    Abstract: Examples described herein relate to a switch configured to allocate packet processing resources, from a pool of packet processing resources, to multiple applications, wherein the pool of packet processing resources comprise configurable packet processing pipelines of one or more network devices and packet processing resources of one or more servers. In some examples, the configurable packet processing pipelines and the packet processing resources are to perform one or more of: network switch operations, microservice communications, and/or block storage operations. In some examples, the network switch operations comprise one or more of: application of at least one access control list (ACL), packet forwarding, packet routing, and/or Virtual Extensible LAN (VXLAN) or GENEVE termination. In some examples, the microservice communications comprise one or more of: packet routing between microservices and/or load balancing of utilized microservices.

    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF
    3.
    发明公开
    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF 审中-公开

    公开(公告)号：US20230362284A1

    公开(公告)日：2023-11-09

    申请号：US18213514

    申请日：2023-06-23

    Applicant: Intel Corporation

    Inventor： Peter P. WASKIEWICZ, JR. ,  Anjali Singhai JAIN ,  Neerav PARIKH ,  Parthasarathy SARANGAM

    IPC: H04L69/22 ,  H04L41/00

    CPC classification number: H04L69/22 ,  H04L41/24

    Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.

    TECHNIQUES FOR CONGESTION MANAGEMENT IN A NETWORK
    4.
    发明申请
    TECHNIQUES FOR CONGESTION MANAGEMENT IN A NETWORK 审中-公开

    公开(公告)号：US20190386924A1

    公开(公告)日：2019-12-19

    申请号：US16517358

    申请日：2019-07-19

    Applicant: Intel Corporation

    Inventor： Arvind SRINIVASAN ,  Ramakrishna HUGGAHALLI ,  Parthasarathy SARANGAM ,  Sunil AHLUWALIA ,  Mrittika GANGULI ,  Malek MUSLEH

    IPC: H04L12/851 ,  H04L12/801 ,  H04L12/803

    Abstract: A switch or network interface can detect congestion caused by a flow of packets. The switch or network interface can generate a congestion hint packet and send the congestion hint packet directly to a source transmitter of the flow of packets that caused the congestion. The congestion hint packet can include information that the source transmitter can use to determine a remedial action to attempt to alleviate or stop congestion at the switch or network interface. For example, the transmitter can reduce a transmit rate of the flow of packets and/or select another route for the flow of packets. Some or all switches or network interfaces between the source transmitter and a destination endpoint can employ flow differentiation whereby a queue is selected to accommodate for a flow's sensitivity to latency.

    NETWORK INTERFACE FOR DATA TRANSPORT IN HETEROGENEOUS COMPUTING ENVIRONMENTS
    5.
    发明申请
    NETWORK INTERFACE FOR DATA TRANSPORT IN HETEROGENEOUS COMPUTING ENVIRONMENTS 审中-公开

    公开(公告)号：US20190297015A1

    公开(公告)日：2019-09-26

    申请号：US16435328

    申请日：2019-06-07

    Applicant: Intel Corporation

    Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

    IPC: H04L12/747 ,  G06F13/28 ,  H04L12/773 ,  G06F12/1081 ,  H04L12/861

    Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

    2 LAYER ALPHA BASED BUFFER MANAGEMENT WITH DYNAMIC RED
    6.
    发明申请
    2 LAYER ALPHA BASED BUFFER MANAGEMENT WITH DYNAMIC RED 有权

    公开(公告)号：US20230056330A1

    公开(公告)日：2023-02-23

    申请号：US17968713

    申请日：2022-10-18

    Applicant: Intel Corporation

    Inventor： Sarig LIVNE ,  Nrupal JANI ,  Eli SHAPIRO ,  Parthasarathy SARANGAM ,  Neerav PARIKH

    IPC: H04L47/11 ,  H04L49/9005

    Abstract: Methods and apparatus for two-layer Alpha-based buffer management with dynamic RED. A two-layer hierarchical sharing scheme using alpha parameters is provided. A buffer is dynamically shared across upper-level entities, such as hosts, using one set of alpha parameters, then a dynamically-adjusted buffer portion allocated for an upper level entity is shared among its lower level entities (e.g., sub queues) using a separate set of low-level alpha parameters. The memory spaces for the upper- and lower-level entities may be dynamically redistributed. Determinations to drop and/or mark and ECN field of received packets are performed using Dynamic RED, which employs dynamic thresholds and associated dynamic probabilities.

    QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD
    7.
    发明申请
    QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD 有权

    公开(公告)号：US20210326177A1

    公开(公告)日：2021-10-21

    申请号：US17359547

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Anil VASUDEVAN ,  Sridhar SAMUDRALA ,  Kiran PATIL ,  Amritha NAMBIAR ,  Parthasarathy SARANGAM

    IPC: G06F9/48 ,  G06F9/52

    Abstract: Examples described herein relate to one or more processors that execute a number of polling threads based on a number of queue identifiers, wherein at least one of the queue identifiers is associated with one or more queues. In some examples, the one or more processors selectively adjust a number of queue identifiers based on a load level of a queue. In some examples, the load level of a queue indicates a number of packets processed per unit of time. In some examples, the number of queue identifiers is no more than a number of configured queues. In some examples, the one or more queues are associated with a queue exclusively allocated to a thread for reading or writing.

    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF
    8.
    发明申请
    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF 审中-公开

    公开(公告)号：US20200274952A1

    公开(公告)日：2020-08-27

    申请号：US16648750

    申请日：2018-09-10

    Applicant: INTEL CORPORATION

    Inventor： Peter P. WASKIEWICZ ,  Anjali Singhai JAIN ,  Neerav PARIKH ,  Parthasarathy SARANGAM

    IPC: H04L29/06 ,  H04L12/24

    Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.

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