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    QUEUE-TO-PORT ALLOCATION
    3.
    发明申请
    QUEUE-TO-PORT ALLOCATION 审中-公开

    公开(公告)号：US20200228467A1

    公开(公告)日：2020-07-16

    申请号：US16833401

    申请日：2020-03-27

    Applicant: Intel Corporation

    Inventor： Eliel LOUZOUN ,  Anjali Singhai JAIN ,  Ben-Zion FRIEDMAN

    IPC: H04L12/861 ,  H04L12/935

    Abstract: Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.

    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF
    4.
    发明公开
    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF 审中-公开

    公开(公告)号：US20230362284A1

    公开(公告)日：2023-11-09

    申请号：US18213514

    申请日：2023-06-23

    Applicant: Intel Corporation

    Inventor： Peter P. WASKIEWICZ, JR. ,  Anjali Singhai JAIN ,  Neerav PARIKH ,  Parthasarathy SARANGAM

    IPC: H04L69/22 ,  H04L41/00

    CPC classification number: H04L69/22 ,  H04L41/24

    Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.

    VIRTUAL DEVICE PORTABILITY
    6.
    发明申请
    VIRTUAL DEVICE PORTABILITY 有权

    公开(公告)号：US20220086226A1

    公开(公告)日：2022-03-17

    申请号：US17483458

    申请日：2021-09-23

    Applicant: Intel Corporation

    Inventor： Anjali Singhai JAIN ,  Noam ELATI ,  Eliel LOUZOUN ,  Daniel DALY

    IPC: H04L67/1097 ,  G06F9/455 ,  G06F13/28

    Abstract: Examples described herein relate to a network interface device comprising: a device interface; at least one processor; a direct memory access (DMA) device; and a packet processing circuitry. In some examples, the at least one processor, when operational, is configured to: in connection with a first operation: perform a format translation of a first descriptor from a first format associated with an emulated device to a second format associated with the packet processing circuitry and provide, to the packet processing circuitry, the translated first descriptor. In some examples, the at least one processor, when operational, is configured to: in connection with a second operation: perform a descriptor format translation of a second descriptor from the second format associated with the packet processing circuitry to the first format associated with the emulated software device and provide, to the emulated device, the translated second descriptor.

    DYNAMIC INTERRUPT PROVISIONING
    7.
    发明申请
    DYNAMIC INTERRUPT PROVISIONING 审中-公开

    公开(公告)号：US20200210359A1

    公开(公告)日：2020-07-02

    申请号：US16814710

    申请日：2020-03-10

    Applicant: Intel Corporation

    Inventor： Linden CORNETT ,  Eliel LOUZOUN ,  Anjali Singhai JAIN ,  Ronen Aharon HYATT ,  Danny VOLKIND ,  Noam ELATI ,  Nadav TURBOVICH

    IPC: G06F13/24 ,  G06F9/48 ,  G06F13/42

    Abstract: Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.

    PAGE FAULT MANAGEMENT TECHNOLOGIES
    9.
    发明申请
    PAGE FAULT MANAGEMENT TECHNOLOGIES 有权

    公开(公告)号：US20220197805A1

    公开(公告)日：2022-06-23

    申请号：US17479954

    申请日：2021-09-20

    Applicant: Intel Corporation

    Inventor： Shaopeng HE ,  Anjali Singhai JAIN ,  Patrick MALONEY ,  Yadong LI ,  Chih-Jen CHANG ,  Kun TIAN ,  Yan ZHAO ,  Rajesh M. SANKARAN ,  Ashok RAJ

    IPC: G06F12/0831 ,  G06F12/1009 ,  G06F9/455

    Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: in connection with a request from a device to copy data to a destination memory address: based on a page fault, copy the data to a backup page and after determination of a virtual-to-physical address translation, copy the data from the backup page to a destination page identified by the physical address. In some examples, the copy the data to a backup page is based on a page fault and an indication that a target buffer for the data is at or above a threshold level of fullness. In some examples, copying the data to a backup page includes: receive the physical address of the backup page from the device and copy data from the device to the backup page based on identification of the backup page.

    NETWORK INTERFACE DEVICE WITH SUPPORT FOR HIERARCHICAL QUALITY OF SERVICE (QOS)
    10.
    发明申请
    NETWORK INTERFACE DEVICE WITH SUPPORT FOR HIERARCHICAL QUALITY OF SERVICE (QOS) 有权

    公开(公告)号：US20210288910A1

    公开(公告)日：2021-09-16

    申请号：US17332815

    申请日：2021-05-27

    Applicant: Intel Corporation

    Inventor： Daniel DALY ,  Anjali Singhai JAIN ,  Chih-Jen CHANG ,  Edmund CHEN ,  Robert HATHAWAY ,  Naru Dames SUNDAR ,  Pawel SZYMANSKI ,  John MANGAN

    IPC: H04L12/815 ,  H04L12/851 ,  H04L12/935

    Abstract: Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS). In some examples, the circuitry is to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on H-QoS comprises a programmable packet processing pipeline that is to be configured to perform one or more of: packet drops of packets received in excess of a receive rate, packet drops based on packet transmission in excess of a transmit rate, and/or traffic shaping of the received packets prior to transmission through one or more output ports. In some examples, to perform packet drops of packets received in excess of a receive rate, the programmable packet processing pipeline is to perform rate limiting per one or more of: class of service, subscriber, service, or interface.

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