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公开(公告)号：US20200371136A1
公开(公告)日：2020-11-26
申请号：US16992947
申请日：2020-08-13
Applicant: Intel Corporation
Inventor： Paul J. Diglio , Joseph F. Walczyk
Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.
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公开(公告)号：US10775414B2
公开(公告)日：2020-09-15
申请号：US15721331
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Paul J. Diglio , Joseph F. Walczyk
Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.
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公开(公告)号：US11674980B2
公开(公告)日：2023-06-13
申请号：US16992947
申请日：2020-08-13
Applicant: Intel Corporation
Inventor： Paul J. Diglio , Joseph F. Walczyk
CPC classification number: G01R1/07364 , G01R1/04 , G01R1/07342 , G01R31/2831 , G01R31/2891
Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.
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公开(公告)号：US20200096567A1
公开(公告)日：2020-03-26
申请号：US16141422
申请日：2018-09-25
Applicant: Intel Corporation
Inventor： Paul J. Diglio , Pooya Tadayon , Karumbu Meyyappan
IPC: G01R31/319 , G01R1/073
Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.
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公开(公告)号：US20230185037A1
公开(公告)日：2023-06-15
申请号：US17548167
申请日：2021-12-10
Applicant: Intel Corporation
Inventor： Eric J. M. Moret , Pooya Tadayon , Karumbu Meyyappan , Paul J. Diglio
IPC: G02B6/42
CPC classification number: G02B6/428 , G02B6/4269 , G02B6/4284
Abstract: An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.
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Patent Agency Ranking
公开(公告)号：US11543454B2
公开(公告)日：2023-01-03
申请号：US16141422
申请日：2018-09-25
Applicant: Intel Corporation
Inventor： Paul J. Diglio , Pooya Tadayon , Karumbu Meyyappan
IPC: G01R31/319 , G01R1/073
Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.
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公开(公告)号：US10393592B2
公开(公告)日：2019-08-27
申请号：US15386768
申请日：2016-12-21
Applicant: Intel Corporation
Inventor： Paul J. Diglio
Abstract: Disclosed is a system for measuring a surface temperature. The system may comprise a printed circuit board, an insulator block, a conductive probe, a plurality of temperature sensors, and a plurality of compressive contact pins. The conductive probe may have a first surface and a second surface opposite the first surface. The conductive probe may be coupled to the insulator block. The plurality of temperature sensors may be coupled to the insulator block and translatable in a first direction within the insulator block. Translation of the plurality of temperature sensors in the first direction may cause each of the plurality of temperature sensors to contact the first surface of the conductive probe. The plurality of compressive contact pins may each be electrically couple a corresponding temperature sensor to the printed circuit board.
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公开(公告)号：US20230095039A1
公开(公告)日：2023-03-30
申请号：US17478337
申请日：2021-09-17
Applicant: Intel Corporation
Inventor： Srikant Nekkanty , Pooya Tadayon , Xavier F. Brun , Wesley B. Morgan , John M. Heck , Joseph F. Walczyk , Paul J. Diglio
IPC: G02B6/26
Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.
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公开(公告)号：US10030916B2
公开(公告)日：2018-07-24
申请号：US14446123
申请日：2014-07-29
Applicant: INTEL CORPORATION
Inventor： Phi Hung Thanh , Paul J. Diglio , John C. Johnson , Jarett L. Rinaldi , Arnab Choudhury
IPC: F28F7/00 , F28F1/10 , F28F3/12 , F28F13/06 , H01L23/473
Abstract: A heat transfer apparatus is described having a manifold. The manifold has a surface having a fluidic exit opening and a fluidic entrance opening. A fluid is to flow from the fluidic exit opening and into the fluidic entrance opening. The manifold has a protrusion emanating from the surface between the fluidic exit opening and the fluidic entrance opening. An apparatus is described having a thermally conductive grooved structure. The thermally conductive grooved structure has a surface having first and second cavities to form first and second fluidic channels. The thermally conductive grooved structure has a protrusion emanating from between the cavities. The protrusion has side surfaces to form parts of the first and second fluidic channels.
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公开(公告)号：US20180172521A1
公开(公告)日：2018-06-21
申请号：US15386768
申请日：2016-12-21
Applicant: Intel Corporation
Inventor： Paul J. Diglio
CPC classification number: G01K1/026 , G01K1/024 , G01K2213/00
Abstract: Disclosed is a system for measuring a surface temperature. The system may comprise a printed circuit board, an insulator block, a conductive probe, a plurality of temperature sensors, and a plurality of compressive contact pins. The conductive probe may have a first surface and a second surface opposite the first surface. The conductive probe may be coupled to the insulator block. The plurality of temperature sensors may be coupled to the insulator block and translatable in a first direction within the insulator block. Translation of the plurality of temperature sensors in the first direction may cause each of the plurality of temperature sensors to contact the first surface of the conductive probe. The plurality of compressive contact pins may each be electrically couple a corresponding temperature sensor to the printed circuit board.
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