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    SELECTABLE-MODE VOLTAGE REGULATOR TOPOLOGY
    2.
    发明申请
    SELECTABLE-MODE VOLTAGE REGULATOR TOPOLOGY 审中-公开
    可选型电压稳压器拓扑学

    公开(公告)号：US20160190921A1

    公开(公告)日：2016-06-30

    申请号：US14582956

    申请日：2014-12-24

    Applicant: Intel Corporation

    Inventor： Pavan Kumar ,  Harish K. Krishnamurthy

    IPC: H02M3/158

    CPC classification number: H02M3/158 ,  H02M3/07 ,  H02M2001/0045

    Abstract: One embodiment provides an apparatus. The apparatus includes a selectable-mode voltage regulator (VR) to implement one or more of a plurality of VR modes. The selectable-mode VR includes a plurality of switches, an inductor (L), a flying capacitor (Cf), and an output capacitor (Cout).

    Abstract translation: 一个实施例提供了一种装置。 该装置包括用于实现多个VR模式中的一个或多个的可选模式电压调节器（VR）。 可选模式VR包括多个开关，电感器（L），飞行电容器（Cf）和输出电容器（Cout）。

    Maintaining proper voltage sequence during sudden power loss
    4.
    发明授权
    Maintaining proper voltage sequence during sudden power loss 有权

    公开(公告)号：US10908665B2

    公开(公告)日：2021-02-02

    申请号：US16225047

    申请日：2018-12-19

    Applicant: Intel Corporation

    Inventor： Horthense D. Tamdem ,  Pavan Kumar

    IPC: G06F1/30 ,  G06F1/28 ,  G05F1/569 ,  G01R19/165 ,  G06F1/26 ,  H02J1/14

    Abstract: Various embodiments comprise a protective circuit to connect at least two voltage rails to each other upon detection of the loss of the supply voltage that provides input power to the voltage regulators. The protective circuit may cause the two outputs of the voltage regulators to be connected to each other through a resistor when such a loss occurs. This in turn may prevent possible circuit damage in the load by preventing the higher output voltage from dropping below the lower output voltage if the capacitors on the outputs of the voltage regulators discharge at different rates. Such a reverse-voltage condition might otherwise cause damage in the load circuitry.

    MAINTAINING PROPER VOLTAGE SEQUENCE DURING SUDDEN POWER LOSS
    5.
    发明申请
    MAINTAINING PROPER VOLTAGE SEQUENCE DURING SUDDEN POWER LOSS 审中-公开

    公开(公告)号：US20190129487A1

    公开(公告)日：2019-05-02

    申请号：US16225047

    申请日：2018-12-19

    Applicant: Intel Corporation

    Inventor： Horthense D. Tamdem ,  Pavan Kumar

    IPC: G06F1/30 ,  G06F1/28 ,  G01R19/165 ,  G05F1/569

    Abstract: Various embodiments comprise a protective circuit to connect at least two voltage rails to each other upon detection of the loss of the supply voltage that provides input power to the voltage regulators. The protective circuit may cause the two outputs of the voltage regulators to be connected to each other through a resistor when such a loss occurs. This in turn may prevent possible circuit damage in the load by preventing the higher output voltage from dropping below the lower output voltage if the capacitors on the outputs of the voltage regulators discharge at different rates. Such a reverse-voltage condition might otherwise cause damage in the load circuitry.

    MULTISOURCE POWER DELIVERY SYSTEM
    8.
    发明申请
    MULTISOURCE POWER DELIVERY SYSTEM 有权
    多功能输电系统

    公开(公告)号：US20160190813A1

    公开(公告)日：2016-06-30

    申请号：US14582969

    申请日：2014-12-24

    Applicant: Intel Corporation

    Inventor： Pavan Kumar

    IPC: H02J5/00 ,  H02J7/00 ,  H02M3/158

    CPC classification number: H02J5/00 ,  H02J7/0016 ,  H02J7/0068 ,  H02J7/34 ,  H02J2007/0059 ,  H02M3/158 ,  H02M3/1582

    Abstract: One embodiment provides an apparatus. The apparatus includes a plurality of storage elements coupled in series. The storage elements are to capture and store energy received from a plurality of sources. The apparatus further includes a balancer coupled to the plurality of storage elements. The balancer is to balance energy drawn from each storage element.

    Abstract translation: 一个实施例提供了一种装置。 该装置包括串联耦合的多个存储元件。 存储元件用于捕获并存储从多个源接收的能量。 该装置还包括耦合到多个存储元件的平衡器。 平衡器用于平衡从每个存储元件抽取的能量。

    SELF-ISOLATION OF POWER-MANAGEMENT INTEGRATED CIRCUITS OF MEMORY MODULES UNDER FAULT CONDITIONS
    10.
    发明公开
    SELF-ISOLATION OF POWER-MANAGEMENT INTEGRATED CIRCUITS OF MEMORY MODULES UNDER FAULT CONDITIONS 审中-公开

    公开(公告)号：US20230168959A1

    公开(公告)日：2023-06-01

    申请号：US17538052

    申请日：2021-11-30

    Applicant: Intel Corporation

    Inventor： Norma Bettine ,  Pavan Kumar ,  Justin Tippetts

    IPC: G06F11/07 ,  G11C5/14

    CPC classification number: G06F11/0754 ,  G06F11/0706 ,  G06F11/0772 ,  G11C5/148 ,  G06F9/4401

    Abstract: Disclosed herein are systems and methods for self-isolation of power-management integrated circuits (PMICs) of memory modules under and in response to fault conditions. In an embodiment, a PMIC is operably engaged with a memory module that is operably engaged with a platform. The memory module includes a non-volatile-memory block having a power supply controlled by the PMIC. The PMIC has a critical-fault signal pin that can be asserted to shut down the platform. The PMIC determines whether at least one critical fault occurred during a prior cycle, and also determines whether a critical fault occurs during a bootup sequence during a current cycle. Based on determining that a prior-cycle critical fault occurred and that a critical fault occurs during the bootup sequence, the PMIC sets a critical-fault indicator corresponding to the current critical fault; powers down the power supply; and does not assert the critical-fault signal pin.

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