公开(公告)号：US10340220B2

公开(公告)日：2019-07-02

申请号：US15748608

申请日：2015-08-26

申请人： Intel Corporation

发明人： Chen-Guan Lee ,  Vadym Kapinus ,  Pei-Chi Liu ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/86 ,  H01L29/786

摘要： IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

公开(公告)号：US10192969B2

公开(公告)日：2019-01-29

申请号：US15327641

申请日：2014-08-19

申请人： Intel Corporation

发明人： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L23/535 ,  H01L23/66 ,  H01L21/3115

摘要： Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US10892192B2

公开(公告)日：2021-01-12

申请号：US15930700

申请日：2020-05-13

申请人： Intel Corporation

发明人： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20190097057A1

公开(公告)日：2019-03-28

申请号：US16203780

申请日：2018-11-29

申请人： Intel Corporation

发明人： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H03D7/16

摘要： An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US10229853B2

公开(公告)日：2019-03-12

申请号：US14914179

申请日：2013-09-27

申请人： Intel Corporation

发明人： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/84 ,  H01L29/66

摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US11335601B2

公开(公告)日：2022-05-17

申请号：US17112959

申请日：2020-12-04

申请人： Intel Corporation

发明人： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US10763209B2

公开(公告)日：2020-09-01

申请号：US15327338

申请日：2014-08-19

申请人： INTEL CORPORATION

发明人： Roman Olac-Vaw ,  Walid Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC分类号： H01L29/78 ,  H01L23/525 ,  H01L29/423 ,  H01L29/66 ,  G11C17/16 ,  H01L21/768 ,  H01L27/112

摘要： A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：US20170207312A1

公开(公告)日：2017-07-20

申请号：US15327641

申请日：2014-08-19

申请人： Intel Corporation

发明人： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC分类号： H01L29/423 ,  H01L23/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/535

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/66 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

摘要： Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US11823954B2

公开(公告)日：2023-11-21

申请号：US17720150

申请日：2022-04-13

申请人： Intel Corporation

发明人： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC分类号： H01L27/12 ,  H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/66

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/7855 ,  H01L29/66545

摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US10692771B2

公开(公告)日：2020-06-23

申请号：US16253760

申请日：2019-01-22

申请人： Intel Corporation

发明人： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC分类号： H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.