公开(公告)号：US20180364792A1

公开(公告)日：2018-12-20

申请号：US15984185

申请日：2018-05-18

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe FIAT ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3265 ,  Y02D10/153 ,  Y02D10/171

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US20180173538A1

公开(公告)日：2018-06-21

申请号：US15896534

申请日：2018-02-14

Applicant: INTEL CORPORATION

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri

IPC: G06F9/4401 ,  G06F1/32 ,  G06F1/26

Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.

公开(公告)号：US20230004209A1

公开(公告)日：2023-01-05

申请号：US17879635

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe FIAT ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US09934048B2

公开(公告)日：2018-04-03

申请号：US15084268

申请日：2016-03-29

Applicant: INTEL CORPORATION

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri

IPC: G06F1/00 ,  G06F9/44 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F9/4411 ,  G06F1/263 ,  G06F1/3212 ,  G06F9/4418

Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.

公开(公告)号：US20170286125A1

公开(公告)日：2017-10-05

申请号：US15084268

申请日：2016-03-29

Applicant: INTEL CORPORATION

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri

IPC: G06F9/44 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F9/4411 ,  G06F1/263 ,  G06F1/3212 ,  G06F9/4418

Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.

公开(公告)号：US09733689B2

公开(公告)日：2017-08-15

申请号：US14752896

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/30 ,  G06F9/52

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/52 ,  Y02D10/171

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

公开(公告)号：US10768680B2

公开(公告)日：2020-09-08

申请号：US15678025

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/00 ,  G06F1/3206 ,  G06F9/30 ,  G06F1/3287 ,  G06F9/52 ,  G06F1/3203

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

公开(公告)号：US10671404B2

公开(公告)日：2020-06-02

申请号：US15896534

申请日：2018-02-14

Applicant: INTEL CORPORATION

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri

IPC: G06F1/24 ,  G06F9/4401 ,  G06F1/26 ,  G06F1/3212 ,  G06F8/65

Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.

公开(公告)号：US10551900B2

公开(公告)日：2020-02-04

申请号：US15471606

申请日：2017-03-28

Applicant: Intel Corporation

Inventor： Vijayakumar A. Dibbad ,  Satish Prathaban ,  Harinarayanan Seshadri ,  Rajeev D. Muralidhar

IPC: G06F1/324 ,  G06F1/3228 ,  G06F1/329

Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.

公开(公告)号：US20180284863A1

公开(公告)日：2018-10-04

申请号：US15471606

申请日：2017-03-28

Applicant: Intel Corporation

Inventor： Vijayakumar A. Dibbad ,  Satish Prathaban ,  Harinarayanan Seshadri ,  Rajeev D. Muralidhar

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/329

Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.