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    AUTONOMOUS AND EXTENSIBLE RESOURCE CONTROL BASED ON SOFTWARE PRIORITY HINT
    2.
    发明申请
    AUTONOMOUS AND EXTENSIBLE RESOURCE CONTROL BASED ON SOFTWARE PRIORITY HINT 有权

    公开(公告)号：US20220206862A1

    公开(公告)日：2022-06-30

    申请号：US17134252

    申请日：2020-12-25

    Applicant: Intel Corporation

    Inventor： Monica Gupta ,  Russell Fenger ,  Andrew J. Herdrich ,  Rajshree Chabukswar ,  Jumnit Hong ,  Sneha Gohad

    IPC: G06F9/50

    Abstract: Embodiments of apparatuses, methods, and systems for resource control based on software priority are described. In embodiments, an apparatus includes resource sharing hardware and multiple cores. The resource sharing hardware is to share the shared resource among the cores. A first core includes first execution circuitry to execute multiple threads. The first core also includes registers programmable by software. A first register is to store a first identifier of a first thread and a first priority tag to indicate a first priority of the first thread relative to a second priority of a second thread. A second register to store a second identifier of the second thread and a second priority tag to indicate the second priority of the second thread relative to the first priority of the first thread. The resource sharing hardware is to use the first priority and the second priority to control access to the shared resource by the first thread and the second thread.

    Precise longitudinal monitoring of memory operations
    3.
    发明授权
    Precise longitudinal monitoring of memory operations 有权

    公开(公告)号：US12216932B2

    公开(公告)日：2025-02-04

    申请号：US18327474

    申请日：2023-06-01

    Applicant: Intel Corporation

    Inventor： Ahmad Yasin ,  Michael Chynoweth ,  Rajshree Chabukswar ,  Muhammad Taher

    IPC: G06F3/06 ,  G06F11/34

    Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

    METHOD AND APPARATUS TO ALLOW ADJUSTMENT OF THE CORE AVAILABILITY MASK PROVIDED TO SYSTEM SOFTWARE
    7.
    发明公开
    METHOD AND APPARATUS TO ALLOW ADJUSTMENT OF THE CORE AVAILABILITY MASK PROVIDED TO SYSTEM SOFTWARE 审中-公开

    公开(公告)号：US20240330050A1

    公开(公告)日：2024-10-03

    申请号：US18193127

    申请日：2023-03-30

    Applicant: Intel Corporation

    Inventor： Madhusudan Chidambaram ,  Efraim Rotem ,  Stephen H. Gunther ,  Rajshree Chabukswar ,  Zhongsheng Wang

    IPC: G06F9/48 ,  G06F9/50

    CPC classification number: G06F9/4893 ,  G06F9/5094

    Abstract: Embodiments herein relate to selecting cores in a processor using a core mask. In one aspect, a computing device includes different types of cores arranged in one or more processors. The core types are different in terms of performance and power consumption. A core mask is provided which indicates the number of cores which are selected to be active for each core type. A driver can receive a gear setting, which represents a first preference for higher performance or reduced power consumption. A slider value, which represents a second preference for higher performance or reduced power consumption, is provided based on the gear setting and a core utilization percentage and/or foreground activity percentage. A core mask is selected based on the slider value and the current workload type. The first preference can guide, without dictating, a decision of which cores are selected.

    METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS
    8.
    发明公开
    METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS 审中-公开

    公开(公告)号：US20240220446A1

    公开(公告)日：2024-07-04

    申请号：US18149072

    申请日：2022-12-30

    Applicant: Intel Corporation

    Inventor： Deepak Samuel Kirubakaran ,  Rajshree Chabukswar ,  Zhongsheng Wang ,  Russell Fenger ,  Asit Kumar Verma ,  DK Deepika ,  Yevgeni Sabin ,  Daniel J. Rogers ,  Cameron T. Rieck

    IPC: G06F15/80 ,  G06F9/48

    CPC classification number: G06F15/80 ,  G06F9/48

    Abstract: Techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platforms are described. In certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).

    Precise longitudinal monitoring of memory operations
    10.
    发明授权
    Precise longitudinal monitoring of memory operations 有权

    公开(公告)号：US10649688B1

    公开(公告)日：2020-05-12

    申请号：US16177642

    申请日：2018-11-01

    Applicant: Intel Corporation

    Inventor： Ahmad Yasin ,  Michael Chynoweth ,  Rajshree Chabukswar ,  Muhammad Taher

    IPC: G06F3/06 ,  G06F11/34

    Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.

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