-
公开(公告)号：US09760158B2
公开(公告)日：2017-09-12
申请号：US14298171
申请日：2014-06-06
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
-
公开(公告)号：US09760160B2
公开(公告)日：2017-09-12
申请号：US14722518
申请日：2015-05-27
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Hisham Abu Salah , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Gal Leibovich , Yevgeni Sabin , Shay Levy
CPC classification number: G06F1/3287 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
-
3.发明申请公开(公告)号：US20250004851A1
公开(公告)日：2025-01-02
申请号：US18344092
申请日：2023-06-29
Applicant: Intel Corporation
Inventor： Yevgeni Sabin , Madhusudan Chidambaram , Refael Mizrahi , Efraim Rotem , Rajshree A. Chabukswar , Eliezer Weissmann , Stephen H. Gunther , Hisham Abu-Salah , Sneha Gohad , Anusha Ramachandran , Praveen Koduru , Hadas Beja , Nofar Mani , Hadar Ringel , Avishai Wagner
Abstract: In one embodiment, a processor includes: at least one first core to execute instructions; at least one second core to execute instructions; and a control circuit coupled to the at least one first core and the at least one second core. The control circuit may be configured to: receive workload telemetry information regarding a workload for execution on the processor; determine a QoS distribution based at least in part on the workload telemetry information; receive a predicted workload type, the predicted workload type based at least in part on the QoS distribution; and cause at least one of the at least one first core or the at least one second core to be parked based on the predicted workload type and the QoS distribution. Other embodiments are described and claimed.
-
4.发明申请公开(公告)号：US20220179473A1
公开(公告)日：2022-06-09
申请号：US17440688
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Chen Ranel , Christopher J. Lake , Hem Doshi , Ido Melamed , Vijay Degalahal , Yevgeni Sabin , Reena Patel , Yoav Ben-Raphael , Nimrod Angel , Efraim Rotem , Shaun Conrad , Tomer Ziv , Nir Rosenzweig , Esfir Natanzon , Yoni Aizik , Arik Gihon , Natanel Abitan
IPC: G06F1/324
Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.
-
公开(公告)号：US20170371400A1
公开(公告)日：2017-12-28
申请号：US15686222
申请日：2017-08-25
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Hisham Abu Salah , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Gal Leibovich , Yevgeni Sabin , Shay Levy
CPC classification number: G06F1/3287 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172 , Y02D10/22
Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
-
Patent Agency Ranking
公开(公告)号：US20240220446A1
公开(公告)日：2024-07-04
申请号：US18149072
申请日：2022-12-30
Applicant: Intel Corporation
Inventor： Deepak Samuel Kirubakaran , Rajshree Chabukswar , Zhongsheng Wang , Russell Fenger , Asit Kumar Verma , DK Deepika , Yevgeni Sabin , Daniel J. Rogers , Cameron T. Rieck
Abstract: Techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platforms are described. In certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).
-
7.发明授权公开(公告)号：US11789516B2
公开(公告)日：2023-10-17
申请号：US17440688
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Chen Ranel , Christopher J. Lake , Hem Doshi , Ido Melamed , Vijay Degalahal , Yevgeni Sabin , Reena Patel , Yoav Ben-Raphael , Nimrod Angel , Efraim Rotem , Shaun Conrad , Tomer Ziv , Nir Rosenzweig , Esfir Natanzon , Yoni Aizik , Arik Gihon , Natanel Abitan
CPC classification number: G06F1/324
Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.
-
公开(公告)号：US10372198B2
公开(公告)日：2019-08-06
申请号：US15686222
申请日：2017-08-25
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Hisham Abu Salah , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Gal Leibovich , Yevgeni Sabin , Shay Levy
IPC: G06F1/26 , G06F1/32 , G06F1/00 , G06F1/3287 , G06F1/324 , G06F1/3234 , G06F1/3296 , G06F9/50
Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
-
公开(公告)号：US10345889B2
公开(公告)日：2019-07-09
申请号：US15668762
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
IPC: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/07
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
-
公开(公告)号：US20180120924A1
公开(公告)日：2018-05-03
申请号：US15668762
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
-
-
-
-
-
-
-
-
-
Search Results
18
records
(took 0.012 seconds)
