公开(公告)号：US11720364B2

公开(公告)日：2023-08-08

申请号：US17033282

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Leeor Peled ,  Refael Mizrahi ,  Amir Leibovitz ,  Jonathan Beimel ,  James Hermerding, II ,  Gilad Olswang ,  Michal Moran ,  Moran Peri ,  Ido Karavany ,  Sudheer Nair ,  Hadas Beja ,  Avishai Wagner ,  Ronen Laperdon

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/30 ,  G06F9/50

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/505 ,  G06F11/3024

Abstract: Disclosed Methods, Apparatus, and articles of manufacture to dynamically enable and/or disable prefetchers are disclosed. An example apparatus include an interface to access telemetry data, the telemetry data corresponding to a counter of a core in a central processing unit, the counter corresponding to a first phase of a workload executed at the central processing unit; a prefetcher state selector to select a prefetcher state for a subsequent phase based on the telemetry data; and the interface to instruct the core in the central processing unit to operate in the subsequent phase according to the prefetcher state.

公开(公告)号：US20190204900A1

公开(公告)日：2019-07-04

申请号：US15859265

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Sudheer Nair ,  James G. Hermerding, II ,  Avinash Ananthakrishnan

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  G06F1/3206

Abstract: Aspects of the embodiments are directed to systems, methods, and program products for rebalancing power in a multi-chip computing platform, which includes a core processor and a discrete peripheral processor. Embodiments include determining that the core processor and the discrete peripheral processor are in a limited usage state; altering a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and polling the core processor and the discrete peripheral processor after an expiration of the second polling time. Embodiments also include using thermal and/or energy consumption data to dynamically adjust polling times to permit the core processor and the discrete peripheral processor to remain in an idle or low power state for as long as possible.

公开(公告)号：US20240045490A1

公开(公告)日：2024-02-08

申请号：US18449890

申请日：2023-08-15

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US11422616B2

公开(公告)日：2022-08-23

申请号：US16830485

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US20210216377A1

公开(公告)日：2021-07-15

申请号：US17213747

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Niharika Arlagadda Narasimharaju ,  Sudheer Nair ,  James Hermerding, II ,  Merwin Brown ,  Deepak Ganapathy ,  Fabian Garita Gonzalez

IPC: G06F9/50 ,  G06F1/28

Abstract: Methods, apparatus, systems and articles of manufacture for power sharing between discrete processors are disclosed. An example apparatus includes a thermal monitor to monitor temperatures of first and second discrete processors and a balance controller to, in response to a first temperature of the first processor satisfying a temperature threshold, adjust first and second power budgets allocated to the respective first and second processors.

公开(公告)号：US12190173B2

公开(公告)日：2025-01-07

申请号：US17213747

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Niharika Arlagadda Narasimharaju ,  Sudheer Nair ,  James Hermerding, II ,  Merwin Brown ,  Deepak Ganapathy ,  Fabian Garita Gonzalez

IPC: G06F9/50 ,  G06F1/28

Abstract: Methods, apparatus, systems and articles of manufacture for power sharing between discrete processors are disclosed. An example apparatus includes a thermal monitor to monitor temperatures of first and second discrete processors and a balance controller to, in response to a first temperature of the first processor satisfying a temperature threshold, adjust first and second power budgets allocated to the respective first and second processors.

公开(公告)号：US20240241559A1

公开(公告)日：2024-07-18

申请号：US18619538

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Rob Sims ,  Deepak Ganapathy ,  Sivasankara Reddy Juturu ,  Sudheer Nair

IPC: G06F1/28 ,  G06F1/3206

CPC classification number: G06F1/28 ,  G06F1/3206

Abstract: Techniques are described for incorporating telemetry related to power source loading and the frequency of power-control events as part of a power balancing algorithm to control an electronic devices' power budgeting among devices sharing a common power source. The techniques utilize telemetry and control loop algorithms to dynamically balance the power between two or more electronic components, which may include a CPU and a GPU. The techniques as described herein function to monitor power source loading as well as the frequency of a predetermined set of events, which may include performance and/or power control events. Based on this information, the power budgets of the devices may be dynamically adjusted up or down to maximize performance, in contrast with the conventional usage of artificial static performance caps.

公开(公告)号：US11775047B2

公开(公告)日：2023-10-03

申请号：US17879256

申请日：2022-08-02

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US20220374066A1

公开(公告)日：2022-11-24

申请号：US17879256

申请日：2022-08-02

Applicant: INTEL CORPORATION

Inventor： JIANFANG ZHU ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US12117886B2

公开(公告)日：2024-10-15

申请号：US18449890

申请日：2023-08-15

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.