公开(公告)号：US20220188016A1

公开(公告)日：2022-06-16

申请号：US17558353

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Virendra Vikramsinh Adsure ,  Taeyoung Kim ,  Chia-Hung S. Kuo ,  Deepak Gandiga Shivakumar ,  Amir Ali Radjai ,  Deepak Samuel Kirubakaran ,  Jianfang Zhu ,  Ivan Chen

IPC: G06F3/06

Abstract: An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.

公开(公告)号：US20250117063A1

公开(公告)日：2025-04-10

申请号：US18972287

申请日：2024-12-06

Applicant: Intel Corporation

Inventor： Kristoffer Fleming ,  Melanie Daniels ,  Paul Diefenbaugh ,  Aleksander Magi ,  Lawrence Falkenstein ,  Raoul Rivas Toledano ,  Vishal Sinha ,  Deepak Samuel Kirubakaran ,  Venkateshan Udhayan ,  Marko Bartscherer ,  Kathy Bui

IPC: G06F1/3231 ,  G06F1/3234 ,  G06N20/00 ,  G06V40/10 ,  G10L15/08 ,  G10L15/18 ,  G10L15/22 ,  G10L15/30 ,  H04N23/65 ,  H04W52/02

Abstract: Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes a microphone to capture audio corresponding to spoken words. The example computing device further includes a speech analyzer to: detect a keyword prompt from among the spoken words, the keyword prompt to precede a query statement of a user of the computing device; and identify topics associated with a subset of the spoken words, the subset of the spoken words captured by the microphone before the keyword prompt. The example computing device also includes a communications interface to, in response to detection of the keyword prompt, transmit information indicative of the query statement and ones of the identified topics to a remote server.

公开(公告)号：US12189452B2

公开(公告)日：2025-01-07

申请号：US17129465

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Kristoffer Fleming ,  Melanie Daniels ,  Paul Diefenbaugh ,  Aleksander Magi ,  Lawrence Falkenstein ,  Raoul Rivas Toledano ,  Vishal Sinha ,  Deepak Samuel Kirubakaran ,  Venkateshan Udhayan ,  Marko Bartscherer ,  Kathy Bui

IPC: G06F1/3231 ,  G06F1/3234 ,  G06N20/00 ,  G06V40/10 ,  G10L15/18 ,  G10L15/22 ,  G10L15/30 ,  H04N23/65 ,  H04W52/02 ,  G10L15/08

Abstract: Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes an image sensor. The example computing device further includes wireless communication circuitry. The example computing device also includes an operations controller to cause the wireless communication circuitry to switch between different operation modes based on an analysis of image data generated by the image sensor. Different ones of the operation modes to consume different amounts of power.

公开(公告)号：US11934249B2

公开(公告)日：2024-03-19

申请号：US17710525

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  Chris Binns ,  Deepak Samuel Kirubakaran ,  Ashraf H Wadaa ,  Rajshree Chabukswar ,  Ahmed Shams ,  Sze Ling Yeap ,  Refael Mizrahi ,  Nicholas Klein

IPC: G06F1/3234 ,  G06F9/50 ,  G06F11/30 ,  G06N20/00

CPC classification number: G06F1/3234 ,  G06F9/5094 ,  G06F11/3062 ,  G06N20/00

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

公开(公告)号：US20220221925A1

公开(公告)日：2022-07-14

申请号：US17710525

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  Chris Binns ,  Deepak Samuel Kirubakaran ,  Ashraf H Wadaa ,  Rajshree Chabukswar ,  Ahmed Shams ,  Sze Ling Yeap ,  Refael Mizrahi ,  Nicholas Klein

IPC: G06F1/3234 ,  G06F11/30 ,  G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

公开(公告)号：US20190102229A1

公开(公告)日：2019-04-04

申请号：US15721858

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Russell J. Fenger ,  Vijay Dhanraj ,  Deepak Samuel Kirubakaran ,  Srividya Ambale ,  Israel Hirsh ,  Eliezer Weissmann ,  Hisham Abu-Salah

IPC: G06F9/50

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

公开(公告)号：US12073227B2

公开(公告)日：2024-08-27

申请号：US17131547

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Noor Mubeen ,  Ashraf H. Wadaa ,  Andrey Gabdulin ,  Russell Fenger ,  Deepak Samuel Kirubakaran ,  Marc Torrant ,  Ryan Thompson ,  Georgina Saborio Dobles ,  Lingjing Zeng

IPC: G06F9/4401 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/4405 ,  G06F9/3877 ,  G06F9/4403 ,  G06F9/5094

Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

公开(公告)号：US20240045490A1

公开(公告)日：2024-02-08

申请号：US18449890

申请日：2023-08-15

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US11733761B2

公开(公告)日：2023-08-22

申请号：US16728899

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Vishal Sinha ,  Paul Diefenbaugh ,  Kristoffer Fleming ,  Raoul Rivas Toledano ,  Deepak Samuel Kirubakaran ,  William Braun

IPC: G06F1/32 ,  G06F1/3231 ,  G06F3/01 ,  G06F3/03

CPC classification number: G06F1/3231 ,  G06F3/013 ,  G06F3/0304

Abstract: Methods and apparatus to manage power and performance of computing devices based on user presence are disclosed. An apparatus includes an engagement detector to determine an engagement of a user with a device based on at least one of image data generated by an image sensor or an application running on the device; and an operation mode selector to select one of a plurality of operation modes for the device based on a level of engagement of the user, the plurality of operation modes including (1) a first operation mode associated with the device operating at a first performance level and a first power level and (2) a second operation mode associated with the device operating at a second performance level and a second power level, the first performance level being higher than the second performance level, the first power level being higher than the second power level.

公开(公告)号：US11422616B2

公开(公告)日：2022-08-23

申请号：US16830485

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.