公开(公告)号：US09384801B2

公开(公告)日：2016-07-05

申请号：US14461154

申请日：2014-08-15

Applicant: INTEL CORPORATION

Inventor： Abhinav Pandey ,  Hanmant P. Belgal ,  Prashant S. Damle ,  Arjun Kripanidhi ,  Sebastian T. Uribe ,  Dany-Sebastien Ly-Gagnon ,  Sanjay Rangan ,  Kiran Pangal

IPC: G11C7/00 ,  G11C7/12 ,  G11C29/50 ,  G06F11/10 ,  G11C14/00 ,  G11C7/04 ,  G11C13/00

CPC classification number: G11C7/12 ,  G06F11/1072 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C14/0045 ,  G11C29/028 ,  G11C29/50004 ,  G11C2013/0057 ,  G11C2029/5004

Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。

公开(公告)号：US20210407616A1

公开(公告)日：2021-12-30

申请号：US16946528

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Sebastian T. Uribe

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/14 ,  G11C29/18

Abstract: A method, apparatus and system. The method includes: storing, in a memory circuitry, information on memory commands and associated addresses, the memory commands including read and write commands corresponding to associated addresses within memory chips of a storage device; in response to a determination of a read failure corresponding to at least one of the memory commands: performing a read operation on the information from the memory circuitry; and causing the information to be sent to a host of a computer system that includes the storage device, the information adapted to be used to implement a memory debugging operation for the memory chips.

公开(公告)号：US11200961B1

公开(公告)日：2021-12-14

申请号：US16946528

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Sebastian T. Uribe

IPC: G11C29/44 ,  G11C29/18 ,  G11C29/14 ,  G11C29/12

Abstract: A method, apparatus and system. The method includes: storing, in a memory circuitry, information on memory commands and associated addresses, the memory commands including read and write commands corresponding to associated addresses within memory chips of a storage device; in response to a determination of a read failure corresponding to at least one of the memory commands: performing a read operation on the information from the memory circuitry; and causing the information to be sent to a host of a computer system that includes the storage device, the information adapted to be used to implement a memory debugging operation for the memory chips.