-
公开(公告)号：US11626161B2
公开(公告)日：2023-04-11
申请号：US17368634
申请日：2021-07-06
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Kyung Jean Yoon , John Gorman , Dany-Sebastien Ly-Gagnon
Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.
-
公开(公告)号：US12153823B2
公开(公告)日：2024-11-26
申请号：US17068369
申请日：2020-10-12
Applicant: Intel Corporation
Inventor： Davide Fugazza , Dany-Sebastien Ly-Gagnon , DerChang Kau
Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.
-
公开(公告)号：US20170053698A1
公开(公告)日：2017-02-23
申请号：US15347736
申请日：2016-11-09
Applicant: Intel Corporation
Inventor： Dany-Sebastien Ly-Gagnon , Kiran Pangal , Raymond W. Zeng , Mase J. Taub
IPC: G11C13/00
CPC classification number: G11C11/00 , G06F11/1048 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C2213/77 , H01L29/06 , H04L65/403
Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。
-
公开(公告)号：US11100987B1
公开(公告)日：2021-08-24
申请号：US16831639
申请日：2020-03-26
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Kyung Jean Yoon , John Gorman , Dany-Sebastien Ly-Gagnon
Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.
-
公开(公告)号：US09543004B1
公开(公告)日：2017-01-10
申请号：US14742316
申请日：2015-06-17
Applicant: Intel Corporation
Inventor： Dany-Sebastien Ly-Gagnon , Kiran Pangal , Raymond W. Zeng , Mase J. Taub
CPC classification number: G11C11/00 , G06F11/1048 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C2213/77 , H01L29/06 , H04L65/403
Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。
-
Patent Agency Ranking
公开(公告)号：US20220180934A1
公开(公告)日：2022-06-09
申请号：US17114980
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Davide Fugazza , Dany-Sebastien Ly-Gagnon
Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells assigned to a plurality of groups, wherein each group is associated with a respective at least one program pulse parameter based on programming responses of memory cells of that group; and access circuitry to program a memory cell of a first group of the plurality of groups to a first program state by applying a program pulse having the at least one program pulse parameter associated with the first group.
-
公开(公告)号：US20220113892A1
公开(公告)日：2022-04-14
申请号：US17068369
申请日：2020-10-12
Applicant: Intel Corporation
Inventor： Davide Fugazza , Dany-Sebastien Ly-Gagnon , DerChang Kau
Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.
-
公开(公告)号：US09384801B2
公开(公告)日：2016-07-05
申请号：US14461154
申请日：2014-08-15
Applicant: INTEL CORPORATION
Inventor： Abhinav Pandey , Hanmant P. Belgal , Prashant S. Damle , Arjun Kripanidhi , Sebastian T. Uribe , Dany-Sebastien Ly-Gagnon , Sanjay Rangan , Kiran Pangal
CPC classification number: G11C7/12 , G06F11/1072 , G11C7/04 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C14/0045 , G11C29/028 , G11C29/50004 , G11C2013/0057 , G11C2029/5004
Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.
Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。
-
公开(公告)号：US20220359030A1
公开(公告)日：2022-11-10
申请号：US17866715
申请日：2022-07-18
Applicant: Intel Corporation
Inventor： Yuanyuan Li , Rakan Maddah , Prashant S. Damle , Dany-Sebastien Ly-Gagnon , Lunkai Zhang
Abstract: Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.
-
公开(公告)号：US09685213B2
公开(公告)日：2017-06-20
申请号：US15347736
申请日：2016-11-09
Applicant: Intel Corporation
Inventor： Dany-Sebastien Ly-Gagnon , Kiran Pangal , Raymond W. Zeng , Mase J. Taub
CPC classification number: G11C11/00 , G06F11/1048 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C2213/77 , H01L29/06 , H04L65/403
Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.014 seconds)
