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公开(公告)号：US20160284399A1
公开(公告)日：2016-09-29
申请号：US14671972
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Prashant S. Damle , Kiran Pangal , Hanmant P. Belgal , Abhinav Pandey
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2013/0083
Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
Abstract translation: 提供了一种装置，包括：多个存储单元; 偏置逻辑与所述多个存储单元中的至少一个存储单元耦合，所述偏置逻辑用于：将第一读取电压施加到所述至少一个存储单元; 并且向所述至少一个存储单元施加第二读取电压，所述第一读取电压高于所述第二读取电压; 以及第一电路，其可操作以在所述偏置逻辑将所述第一读取电压施加到所述至少一个存储器单元之前，浮动耦合到所述至少一个存储器单元的字线。 提供了一种方法，其包括：对至少一个存储单元执行第一读取操作; 以及在所述第一读取操作完成之后对所述至少一个存储器单元执行第二读取操作，其中所述第二读取操作与所述第一读取操作不同。
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公开(公告)号：US09384801B2
公开(公告)日：2016-07-05
申请号：US14461154
申请日：2014-08-15
Applicant: INTEL CORPORATION
Inventor： Abhinav Pandey , Hanmant P. Belgal , Prashant S. Damle , Arjun Kripanidhi , Sebastian T. Uribe , Dany-Sebastien Ly-Gagnon , Sanjay Rangan , Kiran Pangal
CPC classification number: G11C7/12 , G06F11/1072 , G11C7/04 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C14/0045 , G11C29/028 , G11C29/50004 , G11C2013/0057 , G11C2029/5004
Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.
Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。
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公开(公告)号：US09613691B2
公开(公告)日：2017-04-04
申请号：US14671972
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Prashant S. Damle , Kiran Pangal , Hanmant P. Belgal , Abhinav Pandey
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2013/0083
Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
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