中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.013 seconds)

    Techniques to support multiple protocols between computer system interconnects
    1.
    发明授权
    Techniques to support multiple protocols between computer system interconnects 有权

    公开(公告)号：US11095556B2

    公开(公告)日：2021-08-17

    申请号：US15639393

    申请日：2017-06-30

    Applicant: INTEL CORPORATION

    Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

    IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08

    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

    TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM INTERCONNECTS
    3.
    发明申请
    TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM INTERCONNECTS 有权

    公开(公告)号：US20210399982A1

    公开(公告)日：2021-12-23

    申请号：US17391557

    申请日：2021-08-02

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

    IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931

    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

    Managing power consumption in a multi-core processor
    5.
    发明授权
    Managing power consumption in a multi-core processor 有权
    管理多核处理器的功耗

    公开(公告)号：US09075614B2

    公开(公告)日：2015-07-07

    申请号：US13782492

    申请日：2013-03-01

    Applicant: Intel Corporation

    Inventor： Eric Fetzer ,  Reid Riedlinger ,  Don Soltis ,  William Bowhill ,  Satish Shrimali ,  Krishnakanth Sistla ,  Efraim Rotem ,  Rakesh Kumar ,  Vivek Garg ,  Alon Naveh ,  Lokesh Sharma

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

    Abstract translation: 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。

Patent Agency Ranking