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公开(公告)号：US10108212B2
公开(公告)日：2018-10-23
申请号：US14861997
申请日：2015-09-22
Applicant: Intel Corporation
Inventor： Sunghyun Park , Stephen Kim , Krishnan Ravichandran , Sriram R. Vangal , Vivek K. De
Abstract: Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage having a value based on a value of the first voltage, a first loop to provide digital control information to control a switching of the power switching unit in order to maintain a relationship between the value of the second voltage and a value of a reference voltage, and a second loop coupled to the power switching unit and the first loop to calculate a value of energy consumption of at least a portion of the apparatus based at least on the digital control information.
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公开(公告)号：US20220101625A1
公开(公告)日：2022-03-31
申请号：US17549583
申请日：2021-12-13
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Hyochan An , Vivek K. De , Narayan Srinivasa , Farzin G. Guilak , Miguel Bautista Gabriel , Pratik Dasharathkumar Patel
IPC: G06V10/774 , G06V10/74 , G06V10/771 , G06V10/22 , G11C29/42 , G11C29/12 , G06N3/04
Abstract: An integrated circuit (IC) is provided for in-situ anomaly detection. Sensors in the IC generates sensor datasets including information indicating conditions in the IC. A processing unit in the IC uses a sensor dataset and a model to detect and classify the anomaly. The processing unit may filter the sensor dataset, extract features from the filtered sensor dataset, and input the features into the model. The model outputs one or more classifications of the anomaly. A feature may be a distance vector that represents a difference between a data value in the filtered sensor dataset from a reference data value. The model may be a network of bit-cells in the IC. The model may be continuously trained in-situ, i.e., on the IC. The processing unit may provide the classifications to another processing unit in the IC. The other processing unit may mitigate the anomaly based on the classifications.
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3.发明申请公开(公告)号：US20190094931A1
公开(公告)日：2019-03-28
申请号：US15718991
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram R. Vangal
Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.
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公开(公告)号：US20190094897A1
公开(公告)日：2019-03-28
申请号：US15712813
申请日：2017-09-22
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Turbo Majumder , Vivek De
Abstract: Various embodiments of the invention may be used to find a combination of voltage and frequency that results in a minimum amount of energy consumption in a digital system, including energy consumed by the system's voltage regulator (VR). The process may involve finding a separate point of minimum energy consumption for each of several different modes of the VR, where a mode is the ratio of Vin to Vout for that VR. The smallest value of those points may then be selected as the overall minimum. The process for making this determination may be performed in situ while the device is in operation, and may encompass changes in operational temperature, load, and process variations.
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公开(公告)号：US20180299506A1
公开(公告)日：2018-10-18
申请号：US16011356
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Vinayak Honkote , Sriram R. Vangal
IPC: G01R31/3173 , G01R31/317 , G06F1/26 , G06F1/32
Abstract: Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.
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Patent Agency Ranking
公开(公告)号：US11669114B2
公开(公告)日：2023-06-06
申请号：US17528241
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Jayanth Mallanayakanahalli Devaraju , Vivek De , Robert Milstrey , Stephen H. Gunther
IPC: G05F1/46 , G06F16/901 , G06F1/3203 , G06F1/28 , G06F16/90 , G06F1/32
CPC classification number: G05F1/462 , G06F1/28 , G06F1/3203 , G06F16/9017
Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.
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公开(公告)号：US10739804B2
公开(公告)日：2020-08-11
申请号：US15712813
申请日：2017-09-22
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Turbo Majumder , Vivek De
Abstract: Various embodiments of the invention may be used to find a combination of voltage and frequency that results in a minimum amount of energy consumption in a digital system, including energy consumed by the system's voltage regulator (VR). The process may involve finding a separate point of minimum energy consumption for each of several different modes of the VR, where a mode is the ratio of Vin to Vout for that VR. The smallest value of those points may then be selected as the overall minimum. The process for making this determination may be performed in situ while the device is in operation, and may encompass changes in operational temperature, load, and process variations.
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公开(公告)号：US10451675B2
公开(公告)日：2019-10-22
申请号：US16011356
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Vinayak Honkote , Sriram R. Vangal
IPC: G01R31/3173 , G06F1/3206 , G06F1/28 , G06F1/30 , G06F1/3296 , G01R31/317 , G06F1/26
Abstract: Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.
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公开(公告)号：US08990662B2
公开(公告)日：2015-03-24
申请号：US13631937
申请日：2012-09-29
Applicant: Intel Corporation
Inventor： Somnath Paul , Sriram R. Vangal , Michael D. Abbott , Eugene M. Kishinevsky
CPC classification number: G06F11/1443 , H04L1/20 , H04L1/242
Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.
Abstract translation: 弹性沟通技巧。 数据路径存储要通过链接发送到接收节点的数据。 输出级耦合在数据路径和链路之间。 输出级包括双重采样机制，以保留通过链路传送到接收节点的数据副本。 错误检测电路与输出级耦合以检测数据通路或输出级中的瞬态定时误差。 响应于检测到错误，错误检测电路使得输出级发送通过链路发送的数据的副本。
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公开(公告)号：US20220075400A1
公开(公告)日：2022-03-10
申请号：US17528241
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Jayanth Mallanayakanahalli Devaraju , Vivek De , Robert Milstrey , Stephen H. Gunther
IPC: G05F1/46 , G06F16/901 , G06F1/3203 , G06F1/28
Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.
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