公开(公告)号：US12079051B2

公开(公告)日：2024-09-03

申请号：US17832370

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Naoki Matsumura ,  Tod F. Schiff ,  Brian Fritz ,  Chee Lim Nge ,  Jorge Rodriguez

IPC: G06F1/20 ,  G06F1/26 ,  H01M10/617 ,  H01M10/63 ,  H02J7/00

CPC classification number: G06F1/206 ,  G06F1/26 ,  H01M10/617 ,  H01M10/63 ,  H02J7/0063

Abstract: Techniques are provided for operating a computing system in a peak power mode while avoiding increased degradation of a battery. The peak power mode include cycles with peak and off-peak currents. The amplitude and duration of the peak and off-peak currents are governed by a thermal/heat budget of the battery. A processor can read the battery information during usage and calculate one or more parameters which are derived from heat. If a parameter is smaller than a reference value, the processor can update the peak power parameters to provide an increase in peak current/power and/or duration. If a parameter is larger than the reference value, no heat budget is available to provide an increase in peak current/power and/or duration. The thermal/heat budget can be enforced over each cycle of the peak power mode or in a summation over multiple cycles.

公开(公告)号：US10739842B2

公开(公告)日：2020-08-11

申请号：US15477046

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Alexander B. Uan-Zo-Li ,  Muhammad Abozaed ,  Efraim Rotem ,  Tod F. Schiff ,  James G. Hermerding, II ,  Chee Lim Nge

IPC: G06F1/00 ,  G06F1/3296 ,  G06F15/76 ,  G06F1/30 ,  G06F1/3215 ,  G06F1/3287 ,  G06F15/78

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

公开(公告)号：US10423202B2

公开(公告)日：2019-09-24

申请号：US15093042

申请日：2016-04-07

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Tod F. Schiff ,  Doron Rajwan ,  Jeffrey M. Jull ,  James G. Hermerding, II ,  Nir Rosenzweig ,  Maytal Toledano ,  Alexander B. Uan-Zo-Li

IPC: G06F1/26 ,  G08B21/18 ,  G06F1/3212 ,  G06F1/324 ,  G08B25/08

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

公开(公告)号：US11567896B2

公开(公告)日：2023-01-31

申请号：US16916197

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F1/20 ,  G06F15/00 ,  G06F1/3234 ,  G06F9/455 ,  G06F9/50 ,  G06F1/26

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

公开(公告)号：US10706004B2

公开(公告)日：2020-07-07

申请号：US15811848

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F1/32 ,  G06F15/00 ,  G06F1/20 ,  G06F1/3234 ,  G06F9/455 ,  G06F9/50 ,  G06F1/26

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

公开(公告)号：US20180284879A1

公开(公告)日：2018-10-04

申请号：US15477046

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Alexander B. Uan-Zo-Li ,  Muhammad Abozaed ,  Efraim Rotem ,  Tod F. Schiff ,  James G. Hermerding, II ,  Chee Lim Nge

IPC: G06F1/32 ,  G06F15/78

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

公开(公告)号：US10020665B2

公开(公告)日：2018-07-10

申请号：US14282059

申请日：2014-05-20

Applicant: INTEL CORPORATION

Inventor： Alexander B. Uan-Zo-Li ,  Patrick K. Leung ,  Tod F. Schiff ,  Scot Lester

IPC: H02J7/00 ,  G01R31/36

CPC classification number: H02J7/0054 ,  H02J7/0004 ,  H02J7/0068 ,  H02J7/0073

Abstract: An electronic apparatus may include a charger device to obtain information relating to a first battery, and to set a limit of a battery charge current of a second battery based on the obtained information.

公开(公告)号：US20200334193A1

公开(公告)日：2020-10-22

申请号：US16916197

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F15/00 ,  G06F1/20 ,  G06F1/3234 ,  G06F9/455 ,  G06F9/50

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

公开(公告)号：US09842082B2

公开(公告)日：2017-12-12

申请号：US14633455

申请日：2015-02-27

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F1/26 ,  G06F1/00 ,  G06F1/32 ,  G06F15/00 ,  G06F1/20 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F15/00 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3243 ,  G06F9/45541 ,  G06F9/45558 ,  G06F9/5077 ,  G06F2009/4557 ,  Y02D10/152 ,  Y02D10/16

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

公开(公告)号：US20220300051A1

公开(公告)日：2022-09-22

申请号：US17832370

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Naoki Matsumura ,  Tod F. Schiff ,  Brian Fritz ,  Chee Lim Nge ,  Jorge Rodriguez

IPC: G06F1/20 ,  G06F1/26 ,  H01M10/617 ,  H01M10/63 ,  H02J7/00

Abstract: Techniques are provided for operating a computing system in a peak power mode while avoiding increased degradation of a battery. The peak power mode include cycles with peak and off-peak currents. The amplitude and duration of the peak and off-peak currents are governed by a thermal/heat budget of the battery. A processor can read the battery information during usage and calculate one or more parameters which are derived from heat. If a parameter is smaller than a reference value, the processor can update the peak power parameters to provide an increase in peak current/power and/or duration. If a parameter is larger than the reference value, no heat budget is available to provide an increase in peak current/power and/or duration. The thermal/heat budget can be enforced over each cycle of the peak power mode or in a summation over multiple cycles.