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    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES
    4.
    发明申请
    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES 有权

    公开(公告)号：US20220246759A1

    公开(公告)日：2022-08-04

    申请号：US17722142

    申请日：2022-04-15

    Applicant: Intel Corporation

    Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Biswajeet GUHA ,  Tahir GHANI ,  William HSU

    IPC: H01L29/78 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

    NANORIBBON SUB-FIN ISOLATION BY BACKSIDE SI SUBSTRATE REMOVAL ETCH SELECTIVE TO SOURCE AND DRAIN EPITAXY
    7.
    发明申请
    NANORIBBON SUB-FIN ISOLATION BY BACKSIDE SI SUBSTRATE REMOVAL ETCH SELECTIVE TO SOURCE AND DRAIN EPITAXY 有权

    公开(公告)号：US20220416027A1

    公开(公告)日：2022-12-29

    申请号：US17357664

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： William HSU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Anand S. MURTHY ,  Tahir GHANI

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

    Abstract: Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires; and a doped nucleation layer at a base of the epitaxial source or drain structures adjacent to the sub-fin. Where the integrated circuit structure comprises an NMOS transistor, doped nucleation layer comprises a carbon-doped nucleation layer. Where the integrated circuit structure comprises a PMOS transistor, doped nucleation layer comprises a heavy boron-doped nucleation layer.

    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES
    9.
    发明申请
    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES 有权

    公开(公告)号：US20220102557A1

    公开(公告)日：2022-03-31

    申请号：US17549827

    申请日：2021-12-13

    Applicant: Intel Corporation

    Inventor： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

    IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

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