公开(公告)号：US20150348972A1

公开(公告)日：2015-12-03

申请号：US14291094

申请日：2014-05-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

IPC: H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10861 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. The asymmetric stressor enables low leakage current for the body region during charge storage while the drain voltage is low, and enables a body potential coupled to the drain region and a lower threshold voltage for the access transistor during read and write operations.

Abstract translation: 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 不对称应力器在漏极电压低时在电荷存储期间使身体区域具有低的漏电流，并且在读取和写入操作期间使能耦合到漏极区域的体电位和用于存取晶体管的较低阈值电压。

公开(公告)号：US08741780B2

公开(公告)日：2014-06-03

申请号：US13796154

申请日：2013-03-12

Applicant: International Business Machines Corporation

Inventor： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

Abstract translation: 通过在沟槽中提供衬垫，切割有源半导体层中的导电沟道区域，蚀刻导电沟道的侧面，拐角和/或底部，其中底切暴露半导体材料来提供用于减少晶体管泄漏的复古掺杂的结构替代方案 在有源层中，用绝缘体代替导电沟道的去除部分。 传导通道的这种整形增加了相邻电路元件的距离，如果充电，电荷可能会导致电压并导致导通通道区域中的反向通道阈值的变化并且减小了通道的横截面积 通道的传导不能很好地控制; 这两种效应显着降低了晶体管的泄漏。

公开(公告)号：US20150363536A1

公开(公告)日：2015-12-17

申请号：US14306715

申请日：2014-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dureseti Chidambarrao ,  James A. Culp ,  Paul C. Parries ,  Ian P. Stobert

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G03F7/70433 ,  G03F7/70633

Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Abstract translation: 用于在半导体光刻掩模设计工艺流程期间减少重叠误差的装置，方法和计算机程序产品。 该方法获得表示光掩模布局设计的密度特性的数据; 基于所获得的密度特征数据预测应力诱导位移; 并通过指定各个照片掩模设计形状的移位移动来预测补偿预测的位移来校正掩模布局设计数据。 为了获得表示密度特性的数据，该方法合并组合的数据以制作光掩模以获得完整的掩模版场数据集。 合并包括表示密度特征驱动应力效应的数据的合并。 然后计算合并的掩模版数据的密度特性数据。 为了预测应力引起的位移，该方法将所述密度特征数据输入到预测作为密度的函数的位移的编程模型中，并输出预测的移位数据。

公开(公告)号：US20140054664A1

公开(公告)日：2014-02-27

申请号：US14071152

申请日：2013-11-04

Applicant: International Business Machines Corporation

Inventor： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC: H01L27/108

CPC classification number: H01L27/10829 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

Abstract translation: 一种形成沟槽结构的方法，其包括在至少沟槽的侧壁上形成含金属层，以及在所述沟槽内形成未掺杂的半导体填充材料。 未掺杂的半导体填充材料和含金属层通过第一蚀刻凹陷到沟槽内的第一深度。 然后将未掺杂的半导体填充材料凹入到沟槽内的第二深度，其大于具有第二蚀刻的第一深度。 第二蚀刻暴露了含金属层的至少一个侧壁部分。 沟槽填充有掺杂的半导体含有材料填充物，其中掺杂半导体材料填充物与含金属层的至少侧壁部分直接接触。

公开(公告)号：US20130189826A1

公开(公告)日：2013-07-25

申请号：US13796154

申请日：2013-03-12

Applicant: International Business Machines Corporation

Inventor： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Weng ,  Yanli Zhang

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

Abstract translation: 通过在沟槽中提供衬垫，切割有源半导体层中的导电沟道区域，蚀刻导电沟道的侧面，拐角和/或底部，其中底切暴露半导体材料来提供用于减少晶体管泄漏的复古掺杂的结构替代方案 在有源层中，用绝缘体代替导电沟道的去除部分。 传导通道的这种整形增加了相邻电路元件的距离，如果充电，电荷可能会导致电压并导致导通通道区域中的反向通道阈值的变化并且减小了通道的横截面积 通道的传导不能很好地控制; 这两种效应显着降低了晶体管的泄漏。

公开(公告)号：US08963283B2

公开(公告)日：2015-02-24

申请号：US14230039

申请日：2014-03-31

Applicant: International Business Machines Corporation

Inventor： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

IPC: H01L29/00 ,  H01L21/20 ,  H01L21/762 ,  H01L27/108 ,  H01L49/02 ,  G06F17/50 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Abstract translation: 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。

公开(公告)号：US08723243B2

公开(公告)日：2014-05-13

申请号：US14071152

申请日：2013-11-04

Applicant: International Business Machines Corporation

Inventor： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC: H01L27/108

CPC classification number: H01L27/10829 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

Abstract translation: 一种形成沟槽结构的方法，其包括在至少沟槽的侧壁上形成含金属层，以及在所述沟槽内形成未掺杂的半导体填充材料。 未掺杂的半导体填充材料和含金属层通过第一蚀刻凹陷到沟槽内的第一深度。 然后将未掺杂的半导体填充材料凹入到沟槽内的第二深度，其大于具有第二蚀刻的第一深度。 第二蚀刻暴露了含金属层的至少一个侧壁部分。 沟槽填充有掺杂的半导体含有材料填充物，其中掺杂半导体材料填充物与含金属层的至少侧壁部分直接接触。

公开(公告)号：US20150349121A1

公开(公告)日：2015-12-03

申请号：US14476897

申请日：2014-09-04

Applicant: International Business Machines Corporation

Inventor： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

IPC: H01L29/78 ,  H01L27/108

CPC classification number: H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

Abstract translation: 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平面化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

公开(公告)号：US09136321B1

公开(公告)日：2015-09-15

申请号：US14265410

申请日：2014-04-30

Applicant: International Business Machines Corporation

Inventor： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78 ,  H01L21/36 ,  H01L29/66

CPC classification number: H01L27/10802 ,  H01L21/84 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/66636 ,  H01L29/78

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

Abstract translation: 本发明一般涉及半导体器件，更具体地，涉及使用低能离子注入形成结对接区域以减少高密度共享公共接触的相邻FET之间的寄生泄漏和体对体泄漏的结构和方法 存储器技术，例如动态随机存取存储器（DRAM）器件和嵌入式DRAM（eDRAM）器件。 所公开的方法可以包括在使用低能离子注入的半导体绝缘体（SOI）层上形成的沟槽的底部形成接合对接区域，并使用保护层保护相邻结构免受离子散射的损害。

公开(公告)号：US09087927B2

公开(公告)日：2015-07-21

申请号：US14521743

申请日：2014-10-23

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

IPC: H01L49/02 ,  H01L21/84 ,  H01L27/108 ,  H01L29/94 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/84 ,  H01L27/10847 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/945

Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Abstract translation: 在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。 电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。 ％至20重量％ ％。