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公开(公告)号：US12068477B2
公开(公告)日：2024-08-20
申请号：US16679369
申请日：2019-11-11
IPC分类号： H01M4/38 , H01M4/04 , H01M4/1395 , H01M4/36 , H01M4/80
CPC分类号： H01M4/386 , H01M4/0402 , H01M4/1395 , H01M4/366 , H01M4/80
摘要： A method of forming a solid-state lithium ion rechargeable battery may include depositing a metal layer onto a top surface of a substrate, depositing a handle layer onto a top surface of the metal layer, wherein a portion of the handle layer overlaps the metal layer and the substrate, spalling a portion of the substrate thereby forming a spalled substrate layer, porosifying the spalled substrate layer thereby forming a porous substrate layer, depositing an electrolyte layer onto a top surface of the porous substrate layer, wherein the electrolyte layer is in direct contact with the porous substrate layer, and depositing a cathode onto a top surface of the electrolyte layer. The method may include depositing a cathode contact layer onto a top surface of the cathode, wherein the cathode contact layer is in direct contact with the cathode. The porous substrate layer may be made of silicon.
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公开(公告)号：US11805711B2
公开(公告)日：2023-10-31
申请号：US17034057
申请日：2020-09-28
发明人： Ning Li , Joel P. de Souza , Kevin W. Brew , Devendra K. Sadana
CPC分类号： H10N70/231 , H10B63/00 , H10N70/021 , H10N70/063 , H10N70/841 , H10N70/8833
摘要： A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.
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公开(公告)号：US11335899B2
公开(公告)日：2022-05-17
申请号：US16397580
申请日：2019-04-29
IPC分类号： H01M4/133 , H01M4/136 , H01M10/0565 , H01M4/66 , C08K3/04 , C08K5/00 , H01M10/0525 , H01M4/02
摘要： A catholyte-like material including a cathode material and an interfacial additive layer for providing a lithium ion energy storage device having low impedance is disclosed. The interfacial additive layer, which is composed of vapor deposited iodine, is present between the cathode material and an electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the cathode material interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device. The catholyte-like material of the present application can be used to provide a lithium ion energy storage device having high charge/discharge rates and/or high capacity.
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公开(公告)号：US11309585B2
公开(公告)日：2022-04-19
申请号：US16389069
申请日：2019-04-19
IPC分类号： H01M10/39 , H01M10/0562 , H01M10/0525 , H01M4/137 , H01M4/1399 , H01M4/1395 , H01M4/38 , H01M4/131 , H01M4/134 , H01M4/36
摘要： An interfacial additive layer for decreasing the interfacial resistance/impedance of a silicon based electrode-containing device such as, for example, an energy storage device or a micro-resistor, is disclosed. The interfacial additive layer, which is composed of a molten lithium containing salt, is formed between a silicon based electrode and a solid polymer electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.
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公开(公告)号：US20220102626A1
公开(公告)日：2022-03-31
申请号：US17034057
申请日：2020-09-28
发明人： Ning Li , Joel P. de Souza , Kevin W. Brew , Devendra K. Sadana
摘要： A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.
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公开(公告)号：US20210143325A1
公开(公告)日：2021-05-13
申请号：US16682647
申请日：2019-11-13
摘要： A PCM cell is provided that includes a silver (Ag) doped Ge2Sb2Te5 (GST) alloy layer as the PCM material. The PCM cell containing the Ag doped GST alloy layer exhibits a reduced reset state resistance drift as compared to an equivalent PCM cell in which a non-Ag doped GST alloy layer is used. In some embodiments and depending on the Ag dopant concentration of the Ag doped GST alloy layer, a constant reset state resistance or even a negative reset state resistance drift can be obtained.
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公开(公告)号：US10944128B2
公开(公告)日：2021-03-09
申请号：US15474668
申请日：2017-03-30
IPC分类号： H01M10/05 , H01M10/0562 , H01M10/052 , H01M10/04 , H01M2/10 , H01M4/04 , H01M10/0525 , H01M10/0585 , H01M4/525
摘要： A solid-state lithium-based battery is provided in which the formation of lithium islands (i.e., lumps) during a charging/recharging cycle is reduced, or even eliminated. Reduction or elimination of lithium islands (i.e., lumps) can be provided by forming a lithium nucleation enhancement liner between a lithium-based solid-state electrolyte layer and a top electrode of a solid-state lithium based battery.
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公开(公告)号：US10692821B2
公开(公告)日：2020-06-23
申请号：US16138971
申请日：2018-09-22
发明人： Ali Afzali-Ardakani , Joel P. de Souza , Bahman Hekmatshoartabari , Daniel M. Kuchta , Devendra K. Sadana
IPC分类号： H01L23/00 , H01L31/112 , H01L21/762 , H01L31/02 , H01L31/0203 , H01L31/0216 , H01L31/0224 , H01L31/024 , H01L31/0376 , H01L31/14 , H01L31/20 , H01L27/144 , H01L29/49
摘要： Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.
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9.发明申请公开(公告)号：US20190214521A1
公开(公告)日：2019-07-11
申请号：US15867121
申请日：2018-01-10
发明人： Joel P. de Souza , Ning Li , Devendra Sadana , Yao Yao
IPC分类号： H01L31/18 , H01L31/0304 , H01L21/04
摘要： Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.
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10.发明申请公开(公告)号：US20190214475A1
公开(公告)日：2019-07-11
申请号：US16353332
申请日：2019-03-14
发明人： Ning Li , Yun Seog Lee , Joel P. de Souza , Devendra K. Sadana
IPC分类号： H01L29/45 , H01L21/02 , H01L21/768 , H01L29/66
摘要： A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.
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