公开(公告)号：US11328110B2

公开(公告)日：2022-05-10

申请号：US16838073

申请日：2020-04-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juergen Pille ,  Tobias Werner ,  Shankar Kalyanasundaram ,  Rolf Sautter

IPC: G06F30/392 ,  G11C5/02 ,  H01L27/092 ,  H01L27/11 ,  G11C5/06

Abstract: An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.

公开(公告)号：US11171142B2

公开(公告)日：2021-11-09

申请号：US16192905

申请日：2018-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juergen Pille ,  Albert Frisch ,  Tobias Werner ,  Rolf Sautter ,  Dieter Wendel

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/822 ,  H01L23/522 ,  H01L29/10 ,  H01L29/423

Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.

公开(公告)号：US20210312116A1

公开(公告)日：2021-10-07

申请号：US16838073

申请日：2020-04-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juergen Pille ,  Tobias Werner ,  Shankar Kalyanasundaram ,  Rolf Sautter

IPC: G06F30/392 ,  G11C5/02 ,  G11C5/06 ,  H01L27/11 ,  H01L27/092

Abstract: An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.

公开(公告)号：US20200159440A1

公开(公告)日：2020-05-21

申请号：US16733363

申请日：2020-01-03

Applicant: International Business Machines Corporation

Inventor： Martin B. Schmidt ,  Peter Altevogt ,  Wolfgang Gellerich ,  Juergen Pille

IPC: G06F3/06 ,  G11C11/413 ,  G11C7/20 ,  G11C11/56

Abstract: Embodiments of memory block erasure are described herein. An aspect includes determining an initial word line set consisting of a single word line. Another aspect includes activating the single word line such that a first memory cell that is connected to the single word line is erased by the activation. Another aspect includes determining a first word line set consisting of the single word line and one additional word line, and wherein the one additional word line corresponds to a second memory cell have a maximum distance from the first memory cell along a bit line that includes the first memory cell and the second memory cell. Another aspect includes activating the first word line set, such that a respective memory cell that is connected to each of the first word line set is erased by the activation.

公开(公告)号：US10204674B2

公开(公告)日：2019-02-12

申请号：US15851792

申请日：2017-12-22

Applicant: International Business Machines Corporation

Inventor： Thomas Kalla ,  Jens Noack ,  Juergen Pille ,  Philipp Salz

IPC: G11C5/06 ,  G11C11/4072 ,  G11C29/00 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G11C11/406

Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.

公开(公告)号：US20190019548A1

公开(公告)日：2019-01-17

申请号：US15831436

申请日：2017-12-05

Applicant: International Business Machines Corporation

Inventor： Thomas Kalla ,  Jens Noack ,  Juergen Pille ,  Philipp Salz

IPC: G11C11/4072 ,  G11C29/00 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C11/4072 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/222 ,  G11C7/225 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/83

Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.

公开(公告)号：US20190019547A1

公开(公告)日：2019-01-17

申请号：US15647410

申请日：2017-07-12

Applicant: International Business Machines Corporation

Inventor： Thomas Kalla ,  Jens Noack ,  Juergen Pille ,  Philipp Salz

IPC: G11C11/4072 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/00

Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.

公开(公告)号：US10096346B2

公开(公告)日：2018-10-09

申请号：US15653782

申请日：2017-07-19

Applicant: International Business Machines Corporation

Inventor： Alexander Fritsch ,  Michael Kugel ,  Juergen Pille ,  Dieter Wendel

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C5/06 ,  G11C7/02

Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.

公开(公告)号：US09761286B2

公开(公告)日：2017-09-12

申请号：US15245668

申请日：2016-08-24

Applicant: International Business Machines Corporation

Inventor： Alexander Fritsch ,  Michael Kugel ,  Juergen Pille ,  Dieter Wendel

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C5/06 ,  G11C7/02

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/02 ,  G11C7/08 ,  G11C7/14

Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.

公开(公告)号：US09552851B2

公开(公告)日：2017-01-24

申请号：US14840134

申请日：2015-08-31

Applicant: International Business Machines Corporation

Inventor： Alexander Fritsch ,  Michael Kugel ,  Juergen Pille ,  Dieter Wendel

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C7/02

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/02 ,  G11C7/08 ,  G11C7/14

Abstract: A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.

Abstract translation: 电流检测放大器包括参考电流输入端子，控制线输入端子，感测电流输入端子，输出端子，第一NAND门，传输门和每个包括n-FET的两个交叉耦合的反相器。 第一NAND门包括耦合到放大器的输出端的输出端。 传输门包括两个传输终端和一个门终端。 栅极端子耦合到控制线端子。 n-FET的源极分别耦合到感测电流输入端子和参考电流输入端子。 一个发送终端耦合到一个逆变器的输入端子，另一个发送端子耦合到另一个逆变器的输入端子。 第一NAND门的输入端分别连接到控制线端子和反相器的输入端之一。