公开(公告)号：US20040203195A1

公开(公告)日：2004-10-14

申请号：US10833754

申请日：2004-04-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takatoshi Tsujimura ,  Osamu Tokuhiro ,  Mitsuo Morooka ,  Takashi Miyamoto

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L021/336 ,  H01L021/8234 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC分类号： H01L29/78696 ,  H01L29/66765 ,  H01L29/78669

摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。

公开(公告)号：US20030122126A1

公开(公告)日：2003-07-03

申请号：US10331699

申请日：2002-12-30

申请人： International Business Machines Corporation

发明人： Takatoshi Tsujimura ,  Osamu Tokuhiro ,  Mitsuo Morooka ,  Takashi Miyamoto

IPC分类号： H01L029/04

CPC分类号： H01L29/78696 ,  H01L29/66765 ,  H01L29/78669

摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。

公开(公告)号：US20020106839A1

公开(公告)日：2002-08-08

申请号：US10061578

申请日：2002-01-31

申请人： International Business Machines Corporation

发明人： Takatoshi Tsujimura ,  Taroh Hasumi ,  Osamu Tokuhiro ,  Mitsuo Morooka

IPC分类号： H01L021/00

CPC分类号： H01L29/66757 ,  H01L29/78633

摘要： A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.

摘要翻译： 公开了一种薄膜晶体管及其制造方法，其中在无机材料钝化层中的开口之间形成接触孔，并在其上形成有机材料层间绝缘膜。 该方法包括使用该开口作为掩模来蚀刻层间绝缘膜中的开口，用于随后蚀刻钝化层中的自对准开口，并且再次在显影反向工艺中蚀刻层间绝缘膜，以获得具有 平坦的内侧壁。

公开(公告)号：US20040105041A1

公开(公告)日：2004-06-03

申请号：US10617964

申请日：2003-07-11

申请人： International Business Machines Corporation

发明人： Takatoshi Tsujimura ,  Takashi Miyamoto ,  Osamu Tokuhiro ,  Mitsuo Morooka

IPC分类号： G02F001/136

CPC分类号： G02F1/136209 ,  H01L27/124 ,  H01L29/78633

摘要： The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line. More particularly, the present invention is directed to a thin film transistor comprising a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk running from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.

摘要翻译： 本发明减少了薄膜晶体管制造工艺中的必要步骤的数量，并且防止由于来自另一数据线的泄漏电流而产生异常电位。 更具体地，本发明涉及一种薄膜晶体管，其包括设置在预定基板上并以预定图案形成的栅极30，对应于栅极30的图案形成的半导体层， 半导体层和由半导体层插入并以与像素电极25相隔预定间隔配置的信号电极26，信号电极26设置在信号电极防止从相邻信号线32b发生串扰的位置， 32c经由半导体层到达像素电极25。

公开(公告)号：US20040001037A1

公开(公告)日：2004-01-01

申请号：US10392616

申请日：2003-03-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takatoshi Tsujimura ,  Kohichi Miwa ,  Mitsuo Morooka

IPC分类号： G09G003/30

CPC分类号： G09G3/3233 ,  G09G2300/0417 ,  G09G2300/0842 ,  G09G2310/0254 ,  G09G2310/066 ,  G09G2320/0233 ,  G09G2320/043

摘要： A technique to reduce the rate of increase in threshold voltage, i.e. degradation, of an amorphous silicon TFT driving an OLED. A first supply voltage is supplied to a drain of the TFT when a first control voltage is applied to a gate of the TFT to activate the TFT and drive the OLED. However, a second, lower supply voltage is supplied to the drain of the TFT when a second control voltage is applied to the gate of the TFT to deactivate the TFT and turn off the OLED, whereby a voltage differential between the drain and the source when the second control voltage is applied to the gate is substantially lower said first supply voltage. This reduces degradation of the TFT. According to one feature of the present invention, when the TFT is turned off by the absence of voltage applied to its gate, the voltage at the drain of the TFT is reduced to approximately zero to minimize the voltage differential between the drain and the source.

摘要翻译： 降低驱动OLED的非晶硅TFT的阈值电压（即退化）的增加速率的技术。 当向TFT的栅极施加第一控制电压以激活TFT并驱动OLED时，向TFT的漏极提供第一电源电压。 然而，当将第二控制电压施加到TFT的栅极以使TFT去激活并关闭OLED时，向TFT的漏极提供第二较低的电源电压，由此在漏极和源极之间的电压差 施加到栅极的第二控制电压基本上低于所述第一电源电压。 这降低了TFT的劣化。 根据本发明的一个特征，当通过不施加施加到其栅极的电压来关闭TFT时，TFT的漏极处的电压被降低到大约零以使漏极和源极之间的电压差最小化。