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公开(公告)号：US20040266173A1
公开(公告)日：2004-12-30
申请号：US10859378
申请日：2004-06-02
IPC分类号： H01L021/4763
CPC分类号： H01L28/60 , H01L21/288 , H01L21/76841 , H01L28/55 , H01L2924/0002 , H05K3/182 , H05K3/389 , Y10T428/24926 , H01L2924/00
摘要： A method for forming an electrically conductive layer having predetermined patterns for semiconductor devices includes providing a substrate, forming an insulation layer having OH functional groups on the substrate, forming a patterned polymer layer on the insulation layer, etching the insulation layer to create a patterned insulation layer which has the same patterns as the patterned polymer layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a coupling agent which reacts with the OH functional groups, treating the patterned insulation layer with a catalyst-containing solution in which the catalyst reacts with the coupling agent, and depositing electrically conductive material on the patterned insulation layer which is catalytically active.
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公开(公告)号：US20020093017A1
公开(公告)日：2002-07-18
申请号：US09765134
申请日：2001-01-18
IPC分类号： H01L029/04 , H01L031/036 , H01L031/0376 , H01L029/76 , H01L031/20 , H01L031/112 , H01L021/00 , H01L021/84 , H01L027/01 , H01L023/62 , H01L027/12 , H01L031/0392
CPC分类号： H01L29/78633 , H01L21/0237 , H01L21/02532 , H01L21/02672 , H01L27/12 , H01L27/1277 , H01L29/66757
摘要： The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT being formed on a substrate, said top-gate type TFT comprising: an insulating layer deposited on said substrate; a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer; a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode; an ohmic contact layer being formed between said metal-dpoant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound; a gate insulating layer deposited on said poly-Si layer; and a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.
摘要翻译： 本发明公开了半导体器件，薄膜晶体管（TFT）和TFT的形成工艺。 根据本发明的半导体器件包括顶栅型薄膜晶体管（TFT），所述顶栅型TFT形成在衬底上，所述顶栅型TFT包括：沉积在所述衬底上的绝缘层; 由金属 - 掺杂剂化合物形成的源电极和漏电极，所述金属 - 掺杂剂化合物沉积在所述绝缘层上; 沉积在所述绝缘层和所述源电极和所述漏电极上的多晶Si（多晶硅）层; 通过所述掺杂剂从所述金属掺杂剂化合物的迁移而在所述金属掺杂化合物和所述多晶硅层之间形成欧姆接触层; 沉积在所述多晶硅层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅电极，其中所述多晶硅层通过金属诱导的横向结晶而结晶。
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公开(公告)号：US20030197180A1
公开(公告)日：2003-10-23
申请号：US10438725
申请日：2003-05-15
IPC分类号： H01L029/76 , H01L031/036 , H01L031/112
CPC分类号： H01L27/12 , H01L27/124 , H01L27/1248 , H01L29/66765 , Y10S438/90
摘要： The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer being deposited on the layers and having first openings for contact holes; and an interlayer insulator extending along with the passivation layer and having second openings for the contact holes, the first openings and the second openings being aligned each other over the substrate, wherein an electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously through an anisotropic etching process.
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4.发明申请Thin film transistor, liquid crystal display device and method of fabricating the thin film transistor 有权薄膜晶体管，液晶显示装置及制造薄膜晶体管的方法公开(公告)号：US20040203195A1
公开(公告)日：2004-10-14
申请号：US10833754
申请日：2004-04-28
IPC分类号： H01L021/00 , H01L021/84 , H01L021/336 , H01L021/8234 , H01L027/01 , H01L027/12 , H01L031/0392 , C30B001/00 , H01L021/20 , H01L021/36
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/78669
摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。
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公开(公告)号：US20030020999A1
公开(公告)日：2003-01-30
申请号：US10114846
申请日：2002-04-02
发明人： Takatoshi Tsujimura , Koichi Miwa , Hiroshi Suzuki
IPC分类号： G02B026/00
CPC分类号： G06F1/1637 , G06F1/1616 , G06F1/1649 , G06F1/169 , G06F3/0238
摘要： An electrophoretic display is mounted on the surface of the housing of a notebook type personal computer. When an event that requires the user to operate a member occurs, the member and operation information corresponding to that event are searched for, and the searched-for operation information is displayed in a region of the electrophoretic display in the vicinity of the searched-for member. For example, when a termination switch is in a corner of the exterior surface of the cover, for a system termination event, information indicating that the termination switch should be operated is displayed in a region of the electrophoretic display in the vicinity of the termination switch.
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6.发明申请公开(公告)号：US20020190253A1
公开(公告)日：2002-12-19
申请号：US09884726
申请日：2001-06-18
IPC分类号： H01L029/04 , H01L031/036 , H01L031/0376 , H01L031/20 , H01L021/00 , H01L021/84
CPC分类号： H01L27/12 , H01L27/124 , H01L27/1248 , H01L29/66765 , Y10S438/90
摘要： The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer being deposited on the layers and having first openings for contact holes; and an interlayer insulator extending along with the passivation layer and having second openings for the contact holes, the first openings and the second openings being aligned each other over the substrate, wherein an electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously through an anisotropic etching process.
摘要翻译： 本发明公开了一种薄膜晶体管及其通过高各向异性蚀刻工艺形成的方法。 根据本发明的薄膜晶体管包括晶体管元件，其包括栅极电极，栅极绝缘层，半导体层以及源极和漏极电极; 钝化层沉积在层上并具有用于接触孔的第一开口; 以及与所述钝化层一起延伸并具有用于所述接触孔的第二开口的层间绝缘体，所述第一开口和所述第二开口在所述衬底上彼此对准，其中导电层沉积在所述接触孔的内壁上，并且 内壁由第一和第二开口形成，其平滑且连续地通过各向异性蚀刻工艺而逐渐变细。
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公开(公告)号：US20020066900A1
公开(公告)日：2002-06-06
申请号：US09730218
申请日：2000-12-05
IPC分类号： H01L029/04 , H01L031/036 , H01L031/0376 , H01L031/20 , H01L027/01 , H01L027/12 , H01L031/0392
CPC分类号： G02F1/136227 , G02F1/1368
摘要： A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.
摘要翻译： 像素单元具有形成在基板上的薄膜晶体管结构。 在薄膜晶体管结构上图形化信号导体，并且透明导电材料的第一图案化层覆盖信号导体。 第一图案化层提供了在蚀刻薄膜晶体管结构的沟道区域中使用的图案。 介电层形成在像素单元的上方，并且包括通向透明导电材料的第一图案化层的通孔。 第二层透明导电材料延伸穿过通孔以接触第一图案化层，其中第二层与晶体管结构自对准。
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8.发明申请Thin film transistor, liquid crystal display panel, and manufacturing method of thin film transistor 有权薄膜晶体管，液晶显示面板以及薄膜晶体管的制造方法公开(公告)号：US20010043292A1
公开(公告)日：2001-11-22
申请号：US09775974
申请日：2001-02-02
发明人： Takatoshi Tsujimura , Kohichi Miwa
IPC分类号： G02F001/136
CPC分类号： G02F1/1368
摘要： The present invention relates to minimizing a leakage current in a floating island region formed in a thin film transistor, and to maintaining a large ON-current required for an operation of the TFT. More specifically, the present invention is directed to a thin film transistor includes: a gate electrode 18 disposed above an insulating substrate and formed in a predetermined pattern; an a-Si film 16 formed in accordance with the pattern of the gate electrode 18; a source electrode 14 formed via the a-Si film 16; and a drain electrode 15 disposed at a predetermined interval from the source electrode 14. The a-Si film 16 includes a floating island region 22 above which or beneath which the gate electrode 18 is not disposed; and the source electrode 14 and the drain electrode 15 are configured in a manner that a channel length of an OFF-current in the floating island region 22, LOFF, is longer than the channel length of an ON-current formed by the source electrode 14 and the drain electrode 15 located above or beneath the gate electrode 18, LON.
摘要翻译： 本发明涉及使形成在薄膜晶体管中的浮岛区域中的漏电流最小化并保持TFT工作所需的大的导通电流。 更具体地，本发明涉及一种薄膜晶体管，包括：栅极电极18，设置在绝缘基板上并以预定图案形成; 根据栅极电极18的图案形成的a-Si膜16; 经由a-Si膜16形成的源电极14; 以及与源电极14隔开规定间隔设置的漏电极15.A-Si膜16包括浮置岛区域22，栅极电极18未被配置在其上方或下方。 并且源电极14和漏电极15被构造成使得浮岛区域22中的截止电流LOFF的沟道长度比由源电极14形成的导通电流的沟道长度长 位于栅极18上方或下方的漏电极LON。
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9.发明申请Thin film transistor, liquid crystal display device and method of fabricating the thin film transistor 有权薄膜晶体管，液晶显示装置及制造薄膜晶体管的方法公开(公告)号：US20030122126A1
公开(公告)日：2003-07-03
申请号：US10331699
申请日：2002-12-30
IPC分类号： H01L029/04
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/78669
摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。
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公开(公告)号：US20020106839A1
公开(公告)日：2002-08-08
申请号：US10061578
申请日：2002-01-31
IPC分类号： H01L021/00
CPC分类号： H01L29/66757 , H01L29/78633
摘要： A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.
摘要翻译： 公开了一种薄膜晶体管及其制造方法，其中在无机材料钝化层中的开口之间形成接触孔，并在其上形成有机材料层间绝缘膜。 该方法包括使用该开口作为掩模来蚀刻层间绝缘膜中的开口，用于随后蚀刻钝化层中的自对准开口，并且再次在显影反向工艺中蚀刻层间绝缘膜，以获得具有 平坦的内侧壁。
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