公开(公告)号：US20040203195A1

公开(公告)日：2004-10-14

申请号：US10833754

申请日：2004-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takatoshi Tsujimura ,  Osamu Tokuhiro ,  Mitsuo Morooka ,  Takashi Miyamoto

IPC: H01L021/00 ,  H01L021/84 ,  H01L021/336 ,  H01L021/8234 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC classification number: H01L29/78696 ,  H01L29/66765 ,  H01L29/78669

Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

Abstract translation: 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。

公开(公告)号：US20030122126A1

公开(公告)日：2003-07-03

申请号：US10331699

申请日：2002-12-30

Applicant: International Business Machines Corporation

Inventor： Takatoshi Tsujimura ,  Osamu Tokuhiro ,  Mitsuo Morooka ,  Takashi Miyamoto

IPC: H01L029/04

CPC classification number: H01L29/78696 ,  H01L29/66765 ,  H01L29/78669

Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

Abstract translation: 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。

公开(公告)号：US20040105041A1

公开(公告)日：2004-06-03

申请号：US10617964

申请日：2003-07-11

Applicant: International Business Machines Corporation

Inventor： Takatoshi Tsujimura ,  Takashi Miyamoto ,  Osamu Tokuhiro ,  Mitsuo Morooka

IPC: G02F001/136

CPC classification number: G02F1/136209 ,  H01L27/124 ,  H01L29/78633

Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line. More particularly, the present invention is directed to a thin film transistor comprising a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk running from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.

Abstract translation: 本发明减少了薄膜晶体管制造工艺中的必要步骤的数量，并且防止由于来自另一数据线的泄漏电流而产生异常电位。 更具体地，本发明涉及一种薄膜晶体管，其包括设置在预定基板上并以预定图案形成的栅极30，对应于栅极30的图案形成的半导体层， 半导体层和由半导体层插入并以与像素电极25相隔预定间隔配置的信号电极26，信号电极26设置在信号电极防止从相邻信号线32b发生串扰的位置， 32c经由半导体层到达像素电极25。