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    Controllable formation of recessed bottom electrode contact in a memory metallization stack
    1.
    发明授权
    Controllable formation of recessed bottom electrode contact in a memory metallization stack 有权

    公开(公告)号：US11133457B2

    公开(公告)日：2021-09-28

    申请号：US16582187

    申请日：2019-09-25

    申请人： International Business Machines Corporation

    发明人： Raghuveer Patlolla ,  James J. Kelly ,  Chih-Chao Yang

    IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

    摘要： A semiconductor device structure includes an MRAM metallization stack. A via is disposed within a dielectric cap layer that is on and in contact with the metallization stack. A liner is disposed on sidewalls and a bottom surface of the via. A recessed electrode contact is disposed within a portion of the via and in contact with a first part of the liner in contact with sidewalls of the via. A second part of the liner is in contact with the sidewalls is above a top surface of the contact. A method for forming the semiconductor device structure includes forming a via within a MRAM metallization stack. The via exposes a top surface of the second metal layer. An electrode contact is formed within a portion of the via. A cap layer is formed within a remaining portion of the via in contact with a top surface of the electrode contact.

    Metal Interconnect Structures with Self-Forming Sidewall Barrier Layer
    4.
    发明申请
    Metal Interconnect Structures with Self-Forming Sidewall Barrier Layer 审中-公开

    公开(公告)号：US20200294911A1

    公开(公告)日：2020-09-17

    申请号：US16352452

    申请日：2019-03-13

    申请人： International Business Machines Corporation

    发明人： Hari Prasad Amanapu ,  Cornelius Brown Peethala ,  Raghuveer Patlolla ,  Chih-Chao Yang

    IPC分类号： H01L23/522 ,  H01L23/532

    摘要： BEOL and MOL interconnect structures with a self-forming sidewall barrier layer are provided. In one aspect, a method of forming an interconnect structure includes: patterning a feature(s) in a dielectric; selectively forming a metal layer at a bottom of the at least one feature; depositing a liner layer lining the feature(s), wherein the conformal liner layer includes a metal alloy AB; depositing a metal onto the liner layer to form the interconnect structure; and annealing the interconnect structure under conditions sufficient to form a barrier layer including the component B along vertical sidewalls of the feature(s). A method of forming an interconnect structure including a via and a trench on top of the via is also provided, as is an interconnect structure.