公开(公告)号：US09275874B2

公开(公告)日：2016-03-01

申请号：US14015640

申请日：2013-08-30

申请人： GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

发明人： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Donald Canaperi ,  Raghuveer Patlolla

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/321

CPC分类号： H01L21/3212 ,  H01L21/32115 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76883

摘要： Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench.

摘要翻译： 提供了使用用于凹陷金属的化学机械平面化（CMP）的集成电路的方法。 在一个实施例中，用于制造集成电路的方法包括用金属填充沟槽并在沟槽外部形成金属的覆盖层部分。 该方法还包括用蚀刻浆料进行平坦化处理以去除金属的覆盖层部分并使沟槽内的金属凹陷。

公开(公告)号：US20150064903A1

公开(公告)日：2015-03-05

申请号：US14015640

申请日：2013-08-30

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc.

发明人： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Donald Canaperi ,  Raghuveer Patlolla

IPC分类号： H01L21/306

CPC分类号： H01L21/3212 ,  H01L21/32115 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76883

摘要： Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench.

摘要翻译： 提供了使用用于凹陷金属的化学机械平面化（CMP）的集成电路的方法。 在一个实施例中，用于制造集成电路的方法包括用金属填充沟槽并在沟槽外部形成金属的覆盖层部分。 该方法还包括用蚀刻浆料进行平坦化处理以去除金属的覆盖层部分并使沟槽内的金属凹陷。

公开(公告)号：US09087881B2

公开(公告)日：2015-07-21

申请号：US13785934

申请日：2013-03-05

申请人： GLOBALFOUNDRIES Inc.

发明人： Sean X. Lin ,  Xunyuan Zhang ,  Ming He ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

摘要翻译： 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US08883631B1

公开(公告)日：2014-11-11

申请号：US13905271

申请日：2013-05-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Xiuyu Cai

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76804

摘要： One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

摘要翻译： 本文公开的一种说明性方法包括在导电结构之上形成至少一层绝缘材料，形成由绝缘材料层上方的金属构成的图案化硬掩模，执行至少一个蚀刻工艺以在绝缘材料层中限定空腔 形成牺牲材料层以便过度填充空腔，执行至少一个平坦化处理以去除牺牲材料层和图案化的硬掩模的一部分，同时将牺牲材料层的剩余部分留在空腔内， 以及去除位于腔内的牺牲材料层的剩余部分。

公开(公告)号：US08962478B1

公开(公告)日：2015-02-24

申请号：US14079305

申请日：2013-11-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Xunyuan Zhang ,  Kunaljeet Tanwar

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer.

摘要翻译： 提供了形成与Cu互连结构的Ru层相邻的掺杂TaN Cu势垒的方法和所得到的器件。 实施例包括在SiO基ILD中形成空腔; 在空腔中并在ILD上保形地形成掺杂的TaN层; 在掺杂的TaN层上保形地形成Ru层; 在Ru层上沉积Cu并填充空腔; 将Cu，Ru层和掺杂的TaN层平坦化到ILD的上表面; 在Cu，Ru层和掺杂的TaN层上形成电介质盖; 以及形成在电介质盖和掺杂的TaN层之间的填充空间。

公开(公告)号：US20140357079A1

公开(公告)日：2014-12-04

申请号：US13905271

申请日：2013-05-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Xiuyu Cai

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76804

摘要： One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

摘要翻译： 本文公开的一种说明性方法包括在导电结构之上形成至少一层绝缘材料，形成由绝缘材料层上方的金属构成的图案化硬掩模，执行至少一个蚀刻工艺以在绝缘材料层中限定空腔 形成牺牲材料层以便过度填充空腔，执行至少一个平坦化处理以去除牺牲材料层和图案化的硬掩模的一部分，同时将牺牲材料层的剩余部分留在空腔内， 以及去除位于腔内的牺牲材料层的剩余部分。

公开(公告)号：US20140357078A1

公开(公告)日：2014-12-04

申请号：US13904567

申请日：2013-05-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Xunyuan Zhang ,  Xiuyu Cai ,  Kunaljeet Tanwar

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/32134 ,  H01L2221/1063

摘要： One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material that exposes at least a portion of a conductive structure, forming a layer of sacrificial material that covers the exposed portion of the conductive structure, with the layer of sacrificial material in position, performing at least one second etching process to remove the patterned hard mask while leaving the layer of sacrificial material in position within the cavity, and removing the layer of sacrificial material positioned within the cavity.

摘要翻译： 本文公开的一种说明性方法包括在导电结构之上形成至少一层绝缘材料，形成由绝缘材料层上方的金属构成的图案化硬掩模，执行至少一个蚀刻工艺以在绝缘材料层中限定空腔 其暴露导电结构的至少一部分，形成覆盖导电结构的暴露部分的牺牲材料层，其中牺牲材料层在适当位置，执行至少一个第二蚀刻工艺以移除图案化的硬掩模，同时 将牺牲材料层留在空腔内的适当位置，以及去除位于空腔内的牺牲材料层。

公开(公告)号：US09558997B2

公开(公告)日：2017-01-31

申请号：US13729180

申请日：2012-12-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Kunaljeet Tanwar

IPC分类号： H01L21/768 ,  H01L21/3213

CPC分类号： H01L21/76865 ,  H01L21/32134 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843

摘要： Embodiments described herein provide approaches for interconnect formation in a semiconductor device. Specifically, a Cu layer is removed to a top surface of an Ru layer using CMP, the Cu layer is removed to form a recess within each of a plurality of trenches of a dielectric of the semiconductor device, and the Ru layer is removed using an etch process (e.g., a wet etch). An additional CMP is performed to reach the desired target trench height and to planarize the wafer.

摘要翻译： 本文描述的实施例提供了用于半导体器件中的互连形成的方法。 具体地，使用CMP将Cu层除去到Ru层的顶表面，去除Cu层以在半导体器件的电介质的多个沟槽的每一个内形成凹陷，并且使用 蚀刻工艺（例如，湿蚀刻）。 执行附加CMP以达到期望的目标沟槽高度并平坦化晶片。

公开(公告)号：US09299745B2

公开(公告)日：2016-03-29

申请号：US14272916

申请日：2014-05-08

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xunyuan Zhang ,  Sean Xuan Lin ,  Kunaljeet Tanwar

IPC分类号： H01L21/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC分类号： H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.

摘要翻译： 提供了具有磁隧道结（MTJ）结构的集成电路和用于制造具有MTJ结构的集成电路的方法。 用于制造集成电路的示例性方法包括形成与下面的半导体器件电连接的第一导线。 该方法暴露第一导线的表面。 此外，该方法选择性地将导电材料沉积在第一导电线的表面上以形成电极接触。 该方法包括在电极接触件上形成MTJ结构。

公开(公告)号：US08932934B2

公开(公告)日：2015-01-13

申请号：US13903283

申请日：2013-05-28

申请人： GlobalFoundries Inc.

发明人： Moosung M. Chae ,  Errol Todd Ryan ,  Nicholas Vincent Licausi ,  Christian Witt ,  Ailian Zhao ,  Ming He ,  Sean X. Lin ,  Xunyuan Zhang ,  Kunaljeet Tanwar

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/48 ,  H01L21/316 ,  H01L21/02

CPC分类号： H01L21/76831 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76843 ,  H01L2221/1047

摘要： A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

摘要翻译： 提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。 一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。