ALIGNMENT THROUGH TOPOGRAPHY ON INTERMEDIATE COMPONENT FOR MEMORY DEVICE PATTERNING

    公开(公告)号:US20200006655A1

    公开(公告)日:2020-01-02

    申请号:US16019798

    申请日:2018-06-27

    Abstract: An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

    METAL-INSULATOR-METAL CAPACITOR STRUCTURE
    7.
    发明申请

    公开(公告)号:US20170084683A1

    公开(公告)日:2017-03-23

    申请号:US15260682

    申请日:2016-09-09

    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

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