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公开(公告)号：US11876136B2
公开(公告)日：2024-01-16
申请号：US17590193
申请日：2022-02-01
发明人： Yi Song , Praveen Joseph , Andrew Greene , Kangguo Cheng
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/10 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L27/0924 , H01L29/0847 , H01L29/1037 , H01L29/66795 , H01L2029/7858
摘要： Embodiments of the invention are directed to a semiconductor device structure that includes a first channel region over a substrate, a second channel region over the first channel region, and a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is configured such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.
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公开(公告)号：US20230114163A1
公开(公告)日：2023-04-13
申请号：US17485765
申请日：2021-09-27
IPC分类号： H01L29/786 , H01L29/66 , H01L29/423
摘要： A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.
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公开(公告)号：US11489044B2
公开(公告)日：2022-11-01
申请号：US17134667
申请日：2020-12-28
发明人： Zhenxing Bi , Kangguo Cheng , Yi Song , Lijuan Zou
IPC分类号： H01L29/06 , H01L23/532 , H01L21/8234 , H01L21/762 , H01L21/768 , H01L29/165 , H01L29/66 , H01L21/02 , H01L29/78
摘要： Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.
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公开(公告)号：US10903162B2
公开(公告)日：2021-01-26
申请号：US16293237
申请日：2019-03-05
发明人： Liying Jiang , Juntao Li , Chih-Chao Yang , Michael Rizzolo , Yi Song
IPC分类号： H01L21/20 , H01L23/525 , H01L21/02 , H01H69/02
摘要： A method for fabricating an electronic fuse includes forming a recess within a film material to define opposed contact segments and a central fuse segment interconnecting the contact segments and altering the material of the central fuse segment of the film material to increase electrical resistance characteristics of the central fuse segment. The central fuse segment may include defects such as voids created by directing a laser at the central fuse segment as a component of a laser annealing process. Alternatively, and or additionally, the central fuse segment may include dopants implementing via an ion implantation process to increase resistance characteristics of the central fuse segment.
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公开(公告)号：US10833180B2
公开(公告)日：2020-11-10
申请号：US16157518
申请日：2018-10-11
发明人： Yi Song , Junli Wang , Chi-Chun Liu , Liying Jiang
IPC分类号： H01L29/66 , H01L29/205 , H01L21/306 , H01L29/51 , H01L29/78 , H01L21/308 , H01L29/08
摘要： Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.
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公开(公告)号：US20200176332A1
公开(公告)日：2020-06-04
申请号：US16787762
申请日：2020-02-11
IPC分类号： H01L21/8238 , H01L29/66 , H01L21/3105 , H01L21/311 , H01L27/092
摘要： Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
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公开(公告)号：US20200027796A1
公开(公告)日：2020-01-23
申请号：US16585798
申请日：2019-09-27
IPC分类号： H01L21/8238 , H01L21/3105 , H01L29/66 , H01L21/311 , H01L27/092
摘要： Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
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公开(公告)号：US20190385916A1
公开(公告)日：2019-12-19
申请号：US16011864
申请日：2018-06-19
IPC分类号： H01L21/8238 , H01L21/311 , H01L29/66 , H01L21/3105 , H01L27/092
摘要： Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
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公开(公告)号：US11189532B2
公开(公告)日：2021-11-30
申请号：US16714766
申请日：2019-12-15
发明人： Yi Song , Jay W. Strane , Eric Miller , Fee Li Lie , Richard A. Conti
IPC分类号： H01L21/8238 , H01L29/66 , H01L21/308 , H01L21/3065 , H01L21/02 , H01L21/3115 , H01L29/06 , H01L21/3105 , H01L27/092 , H01L21/027 , H01L29/10 , H01L21/311 , H01L29/786
摘要： A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.
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公开(公告)号：US10804262B2
公开(公告)日：2020-10-13
申请号：US16283333
申请日：2019-02-22
发明人： Juntao Li , Kangguo Cheng , Yi Song
IPC分类号： H01L21/02 , H01L27/07 , H01L27/092 , H01L23/522 , H01L21/8238 , H01L49/02
摘要： A semiconductor structure includes a decoupling capacitor on a semiconductor substrate. The decoupling capacitor includes a multilayer stack structure having one or more active regions on a top surface thereof. The semiconductor structure further includes one or more semiconductor devices on the one or more active regions on the decoupling capacitor.
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