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    Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance
    2.
    发明授权
    Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance 有权
    具有零二次电容系数或零线性温度系数电容的交错电容器

    公开(公告)号：US08901710B2

    公开(公告)日：2014-12-02

    申请号：US13778321

    申请日：2013-02-27

    Applicant: International Business Machines Corporation

    Inventor： Frederick G. Anderson ,  Natalie B Feilchenfeld ,  Zhong-Xiang He ,  Theodore J. Letavic ,  Yves T. Ngu

    IPC: H01L21/20 ,  H01L49/02

    CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

    Abstract translation: 公开了一种叉指电容器和交叉指向的垂直原始电容器，每个电容器相对于特定参数具有相对较低（例如，零）的电容系数。 例如，电容器可以具有零线性电容温度系数（Tcc），以将电容变化限制为温度或零净二次电压电容系数（Vcc2），以将电容变化限制为电压的函数。 在任何情况下，由于所使用的介电材料的类型及其各自的厚度，每个电容器可以结合至少两个不同的平板电介质，其具有与特定参数相反的极性电容系数。 结果，不同的电介质板将对彼此抵消的电容器的电容产生相反的影响，使得电容器相对于特定参数具有零净电容系数。

    EMBEDDING SEMICONDUCTOR DEVICES IN SILICON-ON-INSULATOR WAFERS CONNECTED USING THROUGH SILICON VIAS
    4.
    发明申请
    EMBEDDING SEMICONDUCTOR DEVICES IN SILICON-ON-INSULATOR WAFERS CONNECTED USING THROUGH SILICON VIAS 有权
    使用硅六氟化硼连接的绝缘子硅绝缘体嵌入式半导体器件

    公开(公告)号：US20150357325A1

    公开(公告)日：2015-12-10

    申请号：US14296812

    申请日：2014-06-05

    Applicant: International Business Machines Corporation

    Inventor： Yan Ding ,  Vibhor Jain ,  Thomas Kessler ,  Yves T. Ngu ,  Robert M. Rassel ,  Sebastian T. Ventrone

    IPC: H01L27/06 ,  H01L21/768 ,  H01L23/367 ,  H01L21/822 ,  H01L27/12 ,  H01L23/48

    CPC classification number: H01L27/0694 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

    Abstract translation: 在制造绝缘体上硅晶片的方法中，注入一个或多个半导体器件元件，并且在第一半导体晶片的顶表面上形成一个或多个浅沟槽隔离。 在第一半导体晶片的顶表面上沉积第一介电材料层，填充浅沟槽隔离物。 在第二半导体晶片的底面上的电介质材料层与第一半导体晶片的顶部的电介质材料层接合，在第二半导体晶片的顶面上形成有一个以上的半导体装置。 然后，产生连接第二半导体晶片的顶表面上的一个或多个半导体器件和第一半导体晶片的顶表面上的一个或多个半导体器件元件的一个或多个穿过硅通孔。

    INTERDIGITATED CAPACITORS WITH A ZERO QUADRATIC VOLTAGE COEFFICIENT OF CAPACITANCE OR ZERO LINEAR TEMPERATURE COEFFICIENT OF CAPACITANCE
    5.
    发明申请
    INTERDIGITATED CAPACITORS WITH A ZERO QUADRATIC VOLTAGE COEFFICIENT OF CAPACITANCE OR ZERO LINEAR TEMPERATURE COEFFICIENT OF CAPACITANCE 有权
    具有零电压系数的电容器或零线性温度系数电容的互连电容器

    公开(公告)号：US20140239448A1

    公开(公告)日：2014-08-28

    申请号：US13778321

    申请日：2013-02-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  Zhong-Xiang He ,  Theodore J. Letavic ,  Yves T. Ngu

    IPC: H01L49/02

    CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

    Abstract translation: 公开了一种叉指电容器和交叉指向的垂直原始电容器，每个电容器相对于特定参数具有相对较低（例如，零）的电容系数。 例如，电容器可以具有零线性电容温度系数（Tcc），以将电容变化限制为温度或零净二次电压电容系数（Vcc2），以将电容变化限制为电压的函数。 在任何情况下，由于所使用的介电材料的类型及其各自的厚度，每个电容器可以结合至少两个不同的平板电介质，其具有与特定参数相反的极性电容系数。 结果，不同的电介质板将对彼此抵消的电容器的电容产生相反的影响，使得电容器相对于特定参数具有零净电容系数。

    MULTILEVEL WAVEGUIDE STRUCTURE
    6.
    发明申请
    MULTILEVEL WAVEGUIDE STRUCTURE 有权
    多波形结构

    公开(公告)号：US20160377806A1

    公开(公告)日：2016-12-29

    申请号：US14749907

    申请日：2015-06-25

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Brendan S. Harris ,  Vibhor Jain ,  Yves T. Ngu ,  Sebastian T. Ventrone

    IPC: G02B6/125 ,  G02B6/122 ,  G02B6/13 ,  G02B6/12

    CPC classification number: G02B6/125 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/30 ,  G02B2006/12061 ,  G02B2006/12147 ,  G02B2006/12195

    Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.

    Abstract translation: 集成光学结构包括第一晶片层，直接连接到第一晶片层顶部的第一绝缘体层，直接连接到第一绝缘体层顶部的第二晶体层，直接连接到第一晶体层顶部的第二绝缘体层 第二晶片层和直接连接到第二绝缘体层的顶部的第三晶片层。 这种结构包括：位于第二晶片层内的第一光波导; 位于所述第二晶片层内的光耦合器，所述第二绝缘体层和所述第三晶片层; 以及位于第三晶片层内的第二光波导。 光耦合器通过第二绝缘体层将光束从第一光波导传输到第二光波导。

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