公开(公告)号：US09853117B2

公开(公告)日：2017-12-26

申请号：US15342396

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US09741715B2

公开(公告)日：2017-08-22

申请号：US15179992

申请日：2016-06-11

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/70 ,  H01L27/088 ,  H01L27/11 ,  H01L29/16 ,  H01L29/06 ,  H01L21/304 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

公开(公告)号：US20170162582A1

公开(公告)日：2017-06-08

申请号：US15055571

申请日：2016-02-27

Applicant: International Business Machines Corporation ,  GlobalFoundries,Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L27/11 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.

公开(公告)号：US20170162451A1

公开(公告)日：2017-06-08

申请号：US15289158

申请日：2016-10-08

Applicant: International Business Machines Corporation ,  GlobalFoundries,Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/8238 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of the set of fins has respective cut faces located at the fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends on the set of fins of the FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.

公开(公告)号：US09646885B1

公开(公告)日：2017-05-09

申请号：US15224091

申请日：2016-07-29

Applicant: International Business Machines Corporation ,  GlobalFoundries,Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method cuts the fins of a FinFET structure to form a set of exposed fin ends. A plasma nitridation process is performed to the set of exposed fin ends. The plasma nitridation process forms a set of nitride layer covered fin ends. Dielectric material is deposited over the FinFET structure. The dielectric is etched to reveal sidewalls of the fins and the set of nitride layer covered fin ends. The nitride layer prevents epitaxial growth at the set of spacer covered fin ends.

公开(公告)号：US09613958B2

公开(公告)日：2017-04-04

申请号：US14735984

申请日：2015-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20170077259A1

公开(公告)日：2017-03-16

申请号：US15363563

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。

公开(公告)号：US20170077099A1

公开(公告)日：2017-03-16

申请号：US15342396

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US09590074B1

公开(公告)日：2017-03-07

申请号：US14960380

申请日：2015-12-05

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/311 ,  H01L27/11 ,  H01L21/027 ,  H01L21/822 ,  H01L29/78 ,  H01L21/304 ,  H01L21/324

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with patterning a photoresist layer over a semiconductor structure having a set of fin ends on a set of fins of a FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step. In another aspect of the invention, a semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

Abstract translation: 用于防止半导体器件中的外延生长的方法开始于在FinFET结构的一组鳍片上具有一组翅片端的半导体结构上的光致抗蚀剂层图案化。 翅片组通过第一介电材料彼此隔离。 光致抗蚀剂被图案化在鳍片端部上，使得其与FinFET结构的其它区域上的光致抗蚀剂图案不同。 使用光致抗蚀剂图案在一组翅片端部上形成一组介质块。 所述介电块组在随后的外延生长步骤中防止在所述鳍片端部的外延生长。 在本发明的另一方面，一种半导体器件包括一组翅片结构，其鳍片结构的相应垂直表面具有一组翅片端，并且由一组沟槽与其它翅片结构隔开。 每个翅片结构具有比该组沟槽中的电介质材料的顶表面高的顶表面。 一组介电块设置在翅片端部的集合处，所述介电块具有与翅片结构的顶表面上或上方的顶表面水平，所述顶部表面限制在翅片端部处的过度的外延生长。

公开(公告)号：US10283423B2

公开(公告)日：2019-05-07

申请号：US15292184

申请日：2016-10-13

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.