公开(公告)号：US07340706B2

公开(公告)日：2008-03-04

申请号：US11239977

申请日：2005-09-30

申请人： Ilya Golubtsov ,  Stanislav V. Aleshin ,  Ranko Scepanovic ,  Sergei Rodin ,  Marina Medvedeva ,  Sergey V. Uzhakov ,  Evgueny E. Egorov ,  Nadya Strelkova

发明人： Ilya Golubtsov ,  Stanislav V. Aleshin ,  Ranko Scepanovic ,  Sergei Rodin ,  Marina Medvedeva ,  Sergey V. Uzhakov ,  Evgueny E. Egorov ,  Nadya Strelkova

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/705

摘要： The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target layer and the OPC mask layer as either repeating or non-repeating, and for each repeating cell, recognizing geometric points in the target layer to determine quality measuring groups. The method also includes simulating the OPC mask layer based on the quality measuring groups, measuring edge placement errors (EPEs) based on at least one of the geometric points, and providing an EPE layer representing EPEs greater than an EPE threshold.

摘要翻译： 本发明提供了一种用于分析OPC掩模的质量的方法和系统。 该方法包括从目标设计接收目标层，从OPC掩模接收OPC掩模层。 该方法还包括将目标层和OPC掩模层中的至少一个的每个单元分类为重复的或不重复的，并且对于每个重复的单元，识别目标层中的几何点以确定质量测量组。 该方法还包括基于质量测量组模拟OPC掩模层，基于至少一个几何点测量边缘放置误差（EPE），以及提供表示大于EPE阈值的EPE的EPE层。

公开(公告)号：US20070079277A1

公开(公告)日：2007-04-05

申请号：US11239977

申请日：2005-09-30

申请人： Ilya Golubtsov ,  Stanislav Aleshin ,  Ranko Scepanovic ,  Sergei Rodin ,  Marina Medvedeva ,  Sergey Uzhakov ,  Evgueny Egorov ,  Nadya Strelkova

发明人： Ilya Golubtsov ,  Stanislav Aleshin ,  Ranko Scepanovic ,  Sergei Rodin ,  Marina Medvedeva ,  Sergey Uzhakov ,  Evgueny Egorov ,  Nadya Strelkova

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/705

摘要： The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target layer and the OPC mask layer as either repeating or non-repeating, and for each repeating cell, recognizing geometric points in the target layer to determine quality measuring groups. The method also includes simulating the OPC mask layer based on the quality measuring groups, measuring edge placement errors (EPEs) based on at least one of the geometric points, and providing an EPE layer representing EPEs greater than an EPE threshold.

摘要翻译： 本发明提供了一种用于分析OPC掩模的质量的方法和系统。 该方法包括从目标设计接收目标层，从OPC掩模接收OPC掩模层。 该方法还包括将目标层和OPC掩模层中的至少一个的每个单元分类为重复的或不重复的，并且对于每个重复的单元，识别目标层中的几何点以确定质量测量组。 该方法还包括基于质量测量组模拟OPC掩模层，基于至少一个几何点测量边缘放置误差（EPE），以及提供表示大于EPE阈值的EPE的EPE层。

公开(公告)号：US06898780B2

公开(公告)日：2005-05-24

申请号：US10327314

申请日：2002-12-20

申请人： Evgueny E. Egorov ,  Stanislav V. Aleshin ,  Ranko Scepanovic

发明人： Evgueny E. Egorov ,  Stanislav V. Aleshin ,  Ranko Scepanovic

IPC分类号： G03F1/00 ,  G03F1/36 ,  G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68 ,  G06F17/5081

摘要： A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes exploding calls on an element list to generate an expanded element list, defining a local cover area for each call on the expanded element list, classifying congruent local cover areas into corresponding groups, and performing an OPC procedure for one local cover area in each group By defining the local cover area for each call and grouping congruent local cover areas, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local cover areas. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.

摘要翻译： 公开了一种在集成电路（IC）芯片设计上执行光学邻近校正（OPC）的方法和系统。 本发明的系统和方法包括在元素列表上爆炸呼叫以生成扩展元素列表，为扩展元素列表上的每个呼叫定义局部覆盖区域，将全局局部覆盖区域分类成对应的组，以及执行OPC过程 每个组中的一个局部覆盖区域通过定义每个呼叫的局部覆盖区域并对同一个局部覆盖区域进行分组，需要对每组一致的局部覆盖区域执行一个OPC过程（例如，评估和校正）。 由于不对IC芯片设计的重复部分执行OPC，所以要评估的数据量和校正次数大大降低，从而大大节省了计算资源和时间。

公开(公告)号：US5742086A

公开(公告)日：1998-04-21

申请号：US517153

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L29/78 ,  H01L29/41

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US06407434B1

公开(公告)日：2002-06-18

申请号：US08517142

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： H01L2144

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H01L29/0657 ,  H01L2924/0002 ,  H03K19/09441 ,  H03K19/0948 ,  H01L2924/00

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a “tri-ister” is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布线中，用于集成电路的微电子单元的互连端子的电导体优选地在彼此成角度地移位60°的三个方向上延伸。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US06197456B1

公开(公告)日：2001-03-06

申请号：US09233828

申请日：1999-01-19

申请人： Stanislav V. Aleshin ,  Genadij V. Belokopitov ,  Ranko Scepanovic

发明人： Stanislav V. Aleshin ,  Genadij V. Belokopitov ,  Ranko Scepanovic

IPC分类号： G03F900

CPC分类号： G03F1/28 ,  G03F1/30

摘要： A mask is provided which has a complex transmission function and which includes a transparent layer and a non-transparent layer. The transparent layer has three types of phase-shifting elements, each imparting a different phase shift relative to the others, with the phase-shifting elements alternating in both x and y dimensions. The non-transparent layer has holes arranged in an approximately equally spaced grid pattern defined by common points in borders of the phase-shifting elements. Centers of at least two holes in the non-transparent layer have different offsets from their corresponding common points. Also provided is a mask blank which includes a transparent layer and a non-transparent layer. The transparent layer has three types of phase-shifting elements, each imparting a different phase shift relative to the others, with the phase-shifting elements alternating in both x and y dimensions.

摘要翻译： 提供具有复杂传输功能的掩模，其包括透明层和不透明层。 透明层具有三种类型的移相元件，每种移相元件相对于其它元件赋予不同的相移，而移相元件在x和y维度上都是交替的。 非透明层具有以相移元件的边界中的共同点限定的大致相等的格栅图案布置的孔。 不透明层中至少两个孔的中心与其相应的公共点具有不同的偏移。 还提供了包括透明层和不透明层的掩模坯料。 透明层具有三种类型的移相元件，每种移相元件相对于其它元件赋予不同的相移，而移相元件在x和y维度上都是交替的。

公开(公告)号：US6097073A

公开(公告)日：2000-08-01

申请号：US517892

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L29/772

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US5838585A

公开(公告)日：1998-11-17

申请号：US986753

申请日：1997-12-08

申请人： Ranko Scepanovic ,  James S. Koford ,  Valeriy B. Kudryavtsev ,  Stanislav V. Aleshin ,  Alexander E. Andreev ,  Alexander S. Podkolzin

发明人： Ranko Scepanovic ,  James S. Koford ,  Valeriy B. Kudryavtsev ,  Stanislav V. Aleshin ,  Alexander E. Andreev ,  Alexander S. Podkolzin

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： An initial placement of cells, and a routing including wires interconnecting the cells, is provided for a microelectronic integrated circuit. A grid is defined as including a plurality of first gridlines that extend parallel to a first axis, and a plurality of second gridlines that extend parallel to a second axis that is angularly displaced from the first axis. The cells are represented as vertices located at intersections of first and second gridlines, and the wires are represented as edges that extend along the first and second gridlines. Clusters of vertices are created such that each cluster includes vertices located on a respective first gridline. A "cover" is computed as including a minimum block of clusters that are connected to all other clusters by wires extending along the second gridlines. Clusters outside the cover are spatially reordered along the second axis away from the cover in descending order of numbers of wires extending from the clusters along the second gridlines. The placement is then updated and rerouted, and these operations are performed in the opposite direction and the two perpendicular directions. A quality factor, preferably the total wirelength of the routing, is computed and compared to a previous value. The entire operation is iteratively performed until the improvement in quality factor between consecutive iterations becomes less than a predetermined value. Due to the nature of the reordering, the quality factor improves monotonically for each iteration. The rerouting steps can be omitted, and edges defined by bounding boxes constructed around interconnect nets.

摘要翻译： 微电子集成电路提供了单元的初始放置以及包括互连电池的布线的布线。 网格被定义为包括平行于第一轴线延伸的多个第一网格线和平行于从第一轴线成角度地移位的第二轴线延伸的多个第二网格线。 细胞被表示为位于第一和第二网格线的交点处的顶点，并且线被表示为沿着第一和第二网格线延伸的边缘。 创建顶点簇，使得每个簇包括位于相应的第一网格线上的顶点。 “盖”被计算为包括通过沿着第二网格线延伸的线连接到所有其他簇的最小块簇。 盖子之外的群集沿着沿着第二网格线从群集延伸的导线的数量的降序沿着沿着第二轴的空间重新排列。 然后更新和重新路由放置，并且这些操作在相反方向和两个垂直方向上执行。 计算质量因子，优选路由的总线长，并将其与先前值进行比较。 迭代执行整个操作，直到连续迭代之间的质量因子的改善变得小于预定值。 由于重新排序的性质，每个迭代的质量因子单调改善。 可以省略重新路由步骤，并且由互连网构成的边界框定义边。

公开(公告)号：US5835378A

公开(公告)日：1998-11-10

申请号：US560834

申请日：1995-11-20

申请人： Ranko Scepanovic ,  James S. Koford ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin ,  Douglas B. Boyle

发明人： Ranko Scepanovic ,  James S. Koford ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin ,  Douglas B. Boyle

IPC分类号： G06F17/50 ,  G06F9/00 ,  G06F11/00

CPC分类号： G06F17/5072

摘要： A digital computer includes a processor, a memory and a program which operate in combination for inputting a placement of cells for an integrated circuit chip, and a netlist of wiring nets interconnecting the cells. The placement is divided into a plurality of contiguous regions, and cell densities in the regions are computed in accordance with locations of the cells in the placement. Wiring densities in the regions are computed in accordance with the locations of the cells and the netlist. The shapes of the regions are altered to produce altered regions such that cell densities and wiring densities in the altered regions are more level or uniform. The placement is then altered such that the cells occupy locations in the altered regions which are relative to their locations in the original regions. The porosities of the cells can also be computed and used in the computation of the region shapes. The wiring densities are computed by constructing bounding boxes around the wiring nets, and computing horizontal and vertical total heights and widths of bounding boxes that overlap the regions. The altered shapes are generated by computing optimal sizes for the regions for containing the cells and required interconnect wiring, computing new lengths for edges of the regions, and iteratively recomputing new positions for corners of the regions using a mechanical mass-spring model until the system reaches equilibrium.

摘要翻译： 数字计算机包括处理器，存储器和程序，其组合操作用于输入用于集成电路芯片的单元的放置，以及互连单元的布线网的网表。 放置被分成多个连续区域，并且根据放置中的单元格的位置来计算区域中的单元密度。 根据单元格和网表的位置来计算区域中的布线密度。 改变区域的形状以产生改变的区域，使得改变区域中的细胞密度和接线密度更高或均匀。 然后改变放置，使得细胞占据相对于它们在原始区域中的位置的改变区域中的位置。 还可以计算细胞的孔隙率，并用于计算区域形状。 布线密度通过在布线网周围构造边界框，并计算与区域重叠的边界框的水平和垂直总高度和宽度来计算。 改变的形状是通过计算用于包含单元的区域和所需的互连布线，计算区域边缘的新长度以及使用机械质量弹簧模型迭代地重新计算区域的角部的新位置而产生的，直到系统 达到平衡。

公开(公告)号：US5834821A

公开(公告)日：1998-11-10

申请号：US517479

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L27/088 ,  H01L29/78

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在彼此成角度地移位60度的三个方向上延伸。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。