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    OCQPSK modulator and modulating method using 1-bit input FIR filter
    2.
    发明授权
    OCQPSK modulator and modulating method using 1-bit input FIR filter 有权
    OCQPSK调制器和使用1位输入FIR滤波器的调制方法

    公开(公告)号：US06819708B1

    公开(公告)日：2004-11-16

    申请号：US09716185

    申请日：2000-11-17

    申请人： In Gi Lim ,  Suk Ho Lee ,  Kyung Soo Kim ,  Han Jin Cho

    发明人： In Gi Lim ,  Suk Ho Lee ,  Kyung Soo Kim ,  Han Jin Cho

    IPC分类号： H04B169

    CPC分类号： H04L27/2071

    摘要： A modulator for an IMT-2000 synchronous mobile station in a digital telecommunication and modulating method thereof, and more particularly, an OCQPSK modulator using FIR filters, each for performing 1:4 interpolation operations for 4 input data and a modulating method thereof. The orthogonal complex quadrature phase shift keying OCQPSK modulating apparatus uses a 1-bit input FIR filter that includes pseudo noise spreading for bifurcating 1-bit data inputted from input channels and pseudo-spreading the bifurcated 1-bit data, an FIR filter for receiving the 1-bit data and performing a filtering operation for pulse shaping, a gain multiplying block for multiplying filtered data outputted from the FIR filter by a gain for respective channels, and a channel adder block for adding data outputted from the gain multiplying block to output I channel and Q channel signals.

    摘要翻译： 一种用于数字电信中的IMT-2000同步移动台的调制器及其调制方法，更具体地，涉及使用FIR滤波器的OCQPSK调制器，每个用于对4个输入数据进行1：4插值运算及其调制方法。 正交复数正交相移键控OCQPSK调制装置使用包括伪噪声扩展的1比特输入FIR滤波器，用于对从输入通道输入的1比特数据进行分叉，并对分叉的1比特数据进行伪扩展; FIR滤波器，用于接收 1位数据并执行用于脉冲整形的滤波操作，用于将从FIR滤波器输出的滤波数据乘以各通道的增益的增益乘法块和用于将从增益乘法块输出的数据加到输出I的通道加法器块 通道和Q通道信号。

    Low offset automatic frequency tuning circuits for continuous-time filter
    4.
    发明授权
    Low offset automatic frequency tuning circuits for continuous-time filter 有权
    低偏移自动频率调谐电路，用于连续时间滤波

    公开(公告)号：US06400932B1

    公开(公告)日：2002-06-04

    申请号：US09454389

    申请日：1999-12-03

    申请人： Chang Jun Oh ,  Jong Kee Kwon ,  Jong Ryul Lee ,  Won Chul Song ,  Hee Bum Jung ,  Kyung Soo Kim ,  Han Jin Cho ,  Ook Kim

    发明人： Chang Jun Oh ,  Jong Kee Kwon ,  Jong Ryul Lee ,  Won Chul Song ,  Hee Bum Jung ,  Kyung Soo Kim ,  Han Jin Cho ,  Ook Kim

    IPC分类号： H04B118

    CPC分类号： H03H11/0422 ,  H03L7/06

    摘要： The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.

    摘要翻译： 调谐电路技术领域本发明涉及一种调谐电路，更具体地说涉及一种用于连续时间滤波器的调谐电路，其能够精确地确定Gm值，以使由于Gm-C型连续时间滤波器中的工艺变化引起的截止频率的变化最小化， 时间过滤器。 根据本发明，提供了一种频率调谐电路，其包括用于产生从第一参考电压放电到第一预定值的信号的积分装置和从第二参考电压到第二预定值的信号充电; 偏移采样装置，用于通过接收与积分装置中包括的Gm单元的偏移电压相乘的电流来对Gm单元的偏移电压进行采样，并在输出节点和所包括的Gm单元的输入节点之间提供反馈路径; 比较信号发生装置，用于通过将从外部输入的时钟分频，将从第一参考电压放电的信号接收到第一预定值和从第二参考电压到第二预定值的信号充电来产生参考信号， 从积分装置获取值，并比较这些信号的实际交点和目标交点; 以及控制装置，用于通过从比较信号发生装置接收参考信号和比较信号并检测它们之间的相位差，产生控制信号以调节积分装置和偏移采样装置的Gm值。

    Delay circuit for low power ring oscillator
    5.
    发明授权
    Delay circuit for low power ring oscillator 失效
    低功耗环形振荡器的延迟电路

    公开(公告)号：US08188801B2

    公开(公告)日：2012-05-29

    申请号：US12878476

    申请日：2010-09-09

    申请人： Myeung Su Kim ,  Han Jin Cho ,  Joon Hyung Lim ,  Kyung Hee Hong ,  Yong Il Kwon

    发明人： Myeung Su Kim ,  Han Jin Cho ,  Joon Hyung Lim ,  Kyung Hee Hong ,  Yong Il Kwon

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0322 ,  H03K3/012

    摘要： Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

    摘要翻译： 这里公开了一种用于低功率环形振荡器的延迟电路。 延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

    WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION
    7.
    发明申请
    WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION 有权
    具有自我感应功能的无线通信设备

    公开(公告)号：US20100150041A1

    公开(公告)日：2010-06-17

    申请号：US12430313

    申请日：2009-04-27

    申请人： Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

    发明人： Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

    IPC分类号： G08C17/00

    CPC分类号： H04Q9/02 ,  H04Q2209/43 ,  H04Q2209/883

    摘要： Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.

    摘要翻译： 公开了一种具有自感功能的无线通信装置，其可以通过使用唤醒功能而不使用单独的传感器来检测对象。 该无线通信装置包括与形成无线网络的服务器无线通信的通信单元，以及当通信单元处于睡眠模式时，在服务器的控制下唤醒通信单元的唤醒单元，并且感测到 根据反射信号在预设通信范围内对象，该反射信号是从通信单元发送之后由对象反射的信号。

    Crossbar switch architecture for multi-processor SoC platform
    8.
    发明授权
    Crossbar switch architecture for multi-processor SoC platform 有权
    交叉开关架构为多处理器SoC平台

    公开(公告)号：US07554355B2

    公开(公告)日：2009-06-30

    申请号：US11607515

    申请日：2006-12-01

    申请人： June Young Chang ,  Han Jin Cho

    发明人： June Young Chang ,  Han Jin Cho

    IPC分类号： H04L12/50 ,  H03K17/00

    CPC分类号： H04L49/101 ,  H04L49/15 ,  H04L49/45

    摘要： Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

    摘要翻译： 提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易 增加并具有简单的控制结构。 交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与 每行最后一列的多路复用器与该行的输入/输出线连接。