公开(公告)号：US09941226B2

公开(公告)日：2018-04-10

申请号：US14569791

申请日：2014-12-15

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hua Tsai ,  Shyh-Jong Chung ,  Ching-Kuan Lee

IPC: H01L23/66 ,  H01L25/03 ,  H01L23/552 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32104 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/1421 ,  H01L2924/1423 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated millimeter-wave chip package structure including an interposer structure, a millimeter-wave chip and a substrate is provided. The interposer structure includes at least an antenna pattern and at least a plated through-hole structure penetrating through the interposer structure and connected to the at least one antenna pattern. The millimeter-wave chip is electrically connected to the at least antenna pattern located either above or below the millimeter-wave chip through the at least plated through-hole structure.

公开(公告)号：US20220367385A1

公开(公告)日：2022-11-17

申请号：US17547200

申请日：2021-12-09

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ching-Kuan Lee ,  Chao-Jung Chen ,  Ren-Shin Cheng ,  Ang-Ying Lin ,  Po-Chih Chang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/15 ,  H01L21/48 ,  H01L21/56

Abstract: A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.

公开(公告)号：US12027470B2

公开(公告)日：2024-07-02

申请号：US17547200

申请日：2021-12-09

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ching-Kuan Lee ,  Chao-Jung Chen ,  Ren-Shin Cheng ,  Ang-Ying Lin ,  Po-Chih Chang

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/568 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17

Abstract: A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.

公开(公告)号：US20240170473A1

公开(公告)日：2024-05-23

申请号：US18347594

申请日：2023-07-06

Applicant: Industrial Technology Research Institute

Inventor： Hao-Che Kao ,  Wen-Hung Liu ,  Yu-Min Lin ,  Ching-Kuan Lee

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/49822 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0655 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/73 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0665

Abstract: A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US20160172317A1

公开(公告)日：2016-06-16

申请号：US14569791

申请日：2014-12-15

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hua Tsai ,  Shyh-Jong Chung ,  Ching-Kuan Lee

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32104 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/1421 ,  H01L2924/1423 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated millimeter-wave chip package structure including an interposer structure, a millimeter-wave chip and a substrate is provided. The interposer structure includes at least an antenna pattern and at least a plated through-hole structure penetrating through the interposer structure and connected to the at least one antenna pattern. The millimeter-wave chip is electrically connected to the at least antenna pattern located either above or below the millimeter-wave chip through the at least plated through-hole structure.

Abstract translation: 提供一种包括中介层结构，毫米波芯片和基板的集成毫米波芯片封装结构。 插入器结构至少包括天线图案和穿过插入件结构并连接到至少一个天线图案的至少一个电镀通孔结构。 毫米波芯片通过至少镀敷的通孔结构电连接到位于毫米波芯片上方或下方的至少天线图案。