公开(公告)号：US20240105669A1

公开(公告)日：2024-03-28

申请号：US18471441

申请日：2023-09-21

Applicant: Infineon Technologies AG

Inventor： Jens Pohl ,  Uwe Wagner ,  Kristof Bothe ,  Andreas Kohl

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/48 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/45 ,  H01L24/49 ,  H01L24/85 ,  B42D25/29 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/93 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05584 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/45012 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4801 ,  H01L2224/4805 ,  H01L2224/48101 ,  H01L2224/48229 ,  H01L2224/484 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/85947 ,  H01L2224/92247 ,  H01L2924/0665

Abstract: A chip assembly having a carrier having a cavity and at least one carrier contact, a chip arranged in the cavity and having at least one chip contact, and a wirebond wire, which electrically conductively connects the at least one chip contact to the at least one carrier contact, wherein the wirebond wire is flat-pressed in at least one subregion.