公开(公告)号：US12097641B2

公开(公告)日：2024-09-24

申请号：US17214256

申请日：2021-03-26

Applicant: Siltectra GmbH

Inventor： Marko David Swoboda ,  Christian Beyer ,  Franz Schilling ,  Jan Richter

IPC: B28D1/22 ,  B23K26/00 ,  B23K26/53 ,  B23K101/40 ,  B28D5/00 ,  B81C1/00 ,  C03B33/02 ,  C03B33/09 ,  H01L21/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/762 ,  H01L31/18

CPC classification number: B28D1/221 ,  B23K26/0006 ,  B23K26/53 ,  B28D5/0005 ,  B81C1/00634 ,  C03B33/0222 ,  H01L21/02005 ,  H01L21/268 ,  H01L21/304 ,  H01L31/1804 ,  H01L31/1896 ,  B23K2101/40 ,  C03B33/091 ,  H01L21/76251

Abstract: A method for separating a solid-body layer from a donor substrate includes providing a donor substrate having a planar surface, a longitudinal axis orthogonal to the planar surface, and a peripheral surface, and producing modifications within the donor substrate using at least one LASER beam. The at least one LASER beam penetrates the donor substrate via the peripheral surface at an angle not equal to 90° relative to the longitudinal axis of the donor substrate. The method further includes producing a stress-inducing polymer layer on the planar surface of the donor substrate, and producing mechanical stresses in the donor substrate by a thermal treatment of the stress-inducing polymer layer. The mechanical stresses produce a crack for separating the solid-body layer, and wherein the crack propagates along the modifications.

公开(公告)号：US20230235479A1

公开(公告)日：2023-07-27

申请号：US18011949

申请日：2021-05-28

Applicant: SILTRONIC AG

Inventor： Andreas SATTLER ,  Juergen VETTERHOEFFER

IPC: C30B29/06 ,  C30B33/02 ,  C30B15/20 ,  C30B15/22 ,  C30B25/20 ,  H01L21/322 ,  H01L21/02

CPC classification number: C30B29/06 ,  C30B33/02 ,  C30B15/203 ,  C30B15/22 ,  C30B25/20 ,  H01L21/3225 ,  H01L21/02005

Abstract: A semiconductor wafer of single-crystal silicon has an oxygen concentration per new ASTM of not less than 5.0×1017 atoms/cm3 and not more than 6.5×1017 atoms/cm3; a nitrogen concentration per new ASTM of not less than 1.0×1013 atoms/cm3 and not more than 1.0×1014 atoms/cm3;



a front side having a silicon epitaxial layer wherein
the semiconductor wafer has BMDs whose mean size is not more than 10 nm determined by transmission electron microscopy and whose mean density adjacent to the epitaxial layer is not less than 1.0×1011 cm−3, determined by reactive ion etching after having subjected the wafer covered with the epitaxial layer to a heat treatment at a temperature of 780° C. for a period of 3 h and to a heat treatment at a temperature of 600° C. for a period of 10 h.

公开(公告)号：US11655560B2

公开(公告)日：2023-05-23

申请号：US17471641

申请日：2021-09-10

Applicant: GlobalWafers Co., Ltd.

Inventor： Soubir Basak ,  Igor Peidous ,  Carissima Marie Hudson ,  Hyungmin Lee ,  Byungchun Kim ,  Robert J. Falster

IPC: C30B29/06 ,  C30B15/00 ,  C30B15/10 ,  C30B15/30 ,  H01L21/02 ,  H01L21/28

CPC classification number: C30B29/06 ,  C30B15/007 ,  C30B15/10 ,  C30B15/305 ,  H01L21/02005 ,  H01L21/02123 ,  H01L21/28167

Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

公开(公告)号：US20180366389A1

公开(公告)日：2018-12-20

申请号：US16062902

申请日：2016-12-14

Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Abdenacer AIT-MANI ,  Bertrand CHAMBION

IPC: H01L23/373 ,  H01L21/768

CPC classification number: H01L23/3738 ,  H01L21/02005 ,  H01L21/0243 ,  H01L21/02664 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76837 ,  H01L21/76877

Abstract: This method comprises the steps of: a) forming a set of first trenches on the first surface of the wafer; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a CTE α1; d) filling the second trenches with a second material having a CTE α2, and verifying α2>α0 or α2 α0 or α1

公开(公告)号：US20180330981A1

公开(公告)日：2018-11-15

申请号：US16032862

申请日：2018-07-11

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Iris Moder ,  Ingo Muri

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L21/76243 ,  H01L21/02005 ,  H01L21/26533 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/7806

Abstract: According to various embodiments, a method includes: providing a substrate having a first side and a second side opposite the first side; forming a buried layer in and/or over the substrate by implanting a chemical element having a greater electronegativity than the substrate into the first side of the substrate by ion implantation; and thinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

公开(公告)号：US20170352545A1

公开(公告)日：2017-12-07

申请号：US15538898

申请日：2015-11-25

Applicant: SUMCO CORPORATION

Inventor： Ryo HIROSE ,  Ryosuke OKUYAMA ,  Kazunari KURITA

IPC: H01L21/265 ,  H01L21/02 ,  H01L27/146

CPC classification number: H01L21/26566 ,  H01L21/02005 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02447 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/26513 ,  H01L21/3221 ,  H01L21/324 ,  H01L27/1464 ,  H01L27/14687

Abstract: Provided is a method of producing a semiconductor epitaxial wafer having enhanced gettering ability. The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer that is located in a surface portion of the semiconductor wafer and that includes a constituent element of the cluster ions in solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The first step is performed in a state in which a temperature of the semiconductor wafer is maintained at lower than 25° C.

公开(公告)号：US09728395B2

公开(公告)日：2017-08-08

申请号：US14867839

申请日：2015-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L29/66 ,  H01L21/18 ,  H01L21/225 ,  H01L21/28 ,  H01L21/322

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

公开(公告)号：US20160111500A1

公开(公告)日：2016-04-21

申请号：US14981602

申请日：2015-12-28

Applicant: Silicon Genesis Corporation

Inventor： Francois J. HENLEY ,  Sien KANG ,  Albert LAMM

IPC: H01L29/20 ,  H01S5/30 ,  H01L31/0304 ,  H01L33/32

CPC classification number: H01L33/0079 ,  C30B29/06 ,  C30B29/406 ,  C30B33/06 ,  H01L21/02005 ,  H01L21/76254 ,  H01L21/78 ,  H01L29/2003 ,  H01L31/028 ,  H01L31/03044 ,  H01L31/1804 ,  H01L31/1856 ,  H01L33/0054 ,  H01L33/32 ,  H01L33/34 ,  H01S5/3013 ,  H01S5/3027

Abstract: Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise (111) single crystal silicon. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices.

公开(公告)号：US20160104622A1

公开(公告)日：2016-04-14

申请号：US14867839

申请日：2015-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/28 ,  H01L21/322

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

Abstract translation: 一种用于制造衬底晶片100的方法包括提供具有第一侧面（111）和第二侧面（112）的器件晶片（110）; 至少在第二侧（112）的区域（112a）中对器件晶片（110）进行第一高温工艺以减少器件晶片（110）的氧含量; 将器件晶片（110）的第二侧（112）接合到载体晶片（120）的第一侧（121）以形成衬底晶片（100）; 处理衬底晶片（100）的第一侧（101）以减小器件晶片（110）的厚度; 对所述衬底晶片（100）进行第二高温处理以至少减少所述器件晶片（110）的氧含量; 以及在所述第二高温处理之后至少部分地将至少一个半导体部件（140）集成到所述器件晶片（110）中。

公开(公告)号：US20160076168A1

公开(公告)日：2016-03-17

申请号：US14849566

申请日：2015-09-09

Applicant: SIXPOINT MATERIALS, INC. ,  SEOUL SEMICONDUCTOR CO., LTD.

Inventor： Tadao HASHIMOTO

IPC: C30B25/18 ,  C30B29/40 ,  C30B29/20

CPC classification number: C30B25/18 ,  C30B29/406 ,  C30B33/06 ,  H01L21/02005 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02658

Abstract: In one instance, the invention provides a substrate for growing a thick layer of group III nitride. The substrate has a first surface prepared for epitaxial growth of group III nitride and a second surface, opposite to the first surface, having a plurality of grooves. The invention also provides a method of producing a thick layer or a bulk crystal of group III nitride using a grooved substrate. The grooved substrate in one configuration grows a thick layer or a bulk crystal of group III nitride with reduced bow and/or spontaneous separation from the substrate.